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| author | Andrzej Hajda <andrzej.hajda@intel.com> | 2022-11-14 11:38:24 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-11-30 08:44:00 -0800 |
| commit | 04aa64375f48a5d430b5550d9271f8428883e550 (patch) | |
| tree | edf677f29dd9a9eae66a7ac0ce57562354c780f7 /Documentation | |
| parent | 01f856ae6d0ca5ad0505b79bf2d22d7ca439b2a1 (diff) | |
| download | linux-04aa64375f48a5d430b5550d9271f8428883e550.tar.bz2 | |
drm/i915: fix TLB invalidation for Gen12 video and compute engines
In case of Gen12 video and compute engines, TLB_INV registers are masked -
to modify one bit, corresponding bit in upper half of the register must
be enabled, otherwise nothing happens.
CVE: CVE-2022-4139
Suggested-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Cc: stable@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions