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authorBjorn Helgaas <bhelgaas@google.com>2019-10-08 15:28:00 -0500
committerBjorn Helgaas <bhelgaas@google.com>2019-11-20 17:33:46 -0600
commit85a9b0507db2fbbfe7912dc3b33d322f200e2ca7 (patch)
tree31cec9768bc0e39466f2c7bd7d5e96815f2c12d9 /Documentation/power
parent6da2f2ccfd2deb81a63fc23a505ccd72de005c39 (diff)
downloadlinux-85a9b0507db2fbbfe7912dc3b33d322f200e2ca7.tar.bz2
PCI/PM: Note that PME can be generated from D0
Per PCIe r5.0 sec 7.5.2.1, PME may be generated from D0, so update Documentation/power/pci.rst to reflect that. Link: https://lore.kernel.org/r/20191016194450.68959-1-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'Documentation/power')
-rw-r--r--Documentation/power/pci.rst4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/power/pci.rst b/Documentation/power/pci.rst
index 1525c594d631..8a4abb7c7363 100644
--- a/Documentation/power/pci.rst
+++ b/Documentation/power/pci.rst
@@ -130,8 +130,8 @@ a full power-on reset sequence and the power-on defaults are restored to the
device by hardware just as at initial power up.
PCI devices supporting the PCI PM Spec can be programmed to generate PMEs
-while in a low-power state (D1-D3), but they are not required to be capable
-of generating PMEs from all supported low-power states. In particular, the
+while in any power state (D0-D3), but they are not required to be capable
+of generating PMEs from all supported power states. In particular, the
capability of generating PMEs from D3cold is optional and depends on the
presence of additional voltage (3.3Vaux) allowing the device to remain
sufficiently active to generate a wakeup signal.