diff options
author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2018-09-05 18:49:44 +0900 |
---|---|---|
committer | Kishon Vijay Abraham I <kishon@ti.com> | 2018-09-25 16:10:07 +0530 |
commit | 74c60cd96b5c8b63be69881fa7da514eae240744 (patch) | |
tree | b8b7a9b8daa589b88bf2287039eb4fcc71c257fe /Documentation/devicetree/bindings | |
parent | ac9ba7dc8613773b037a96af24f381ef230ef1ae (diff) | |
download | linux-74c60cd96b5c8b63be69881fa7da514eae240744.tar.bz2 |
dt-bindings: phy: add UniPhier PCIe PHY description
Add DT bindings for PHY interface built into PCIe controller implemented
in UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r-- | Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt new file mode 100644 index 000000000000..1889d3b89d68 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt @@ -0,0 +1,31 @@ +Socionext UniPhier PCIe PHY bindings + +This describes the devicetree bindings for PHY interface built into +PCIe controller implemented on Socionext UniPhier SoCs. + +Required properties: +- compatible: Should contain one of the following: + "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY + "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY +- reg: Specifies offset and length of the register set for the device. +- #phy-cells: Must be zero. +- clocks: A phandle to the clock gate for PCIe glue layer including + this phy. +- resets: A phandle to the reset line for PCIe glue layer including + this phy. + +Optional properties: +- socionext,syscon: A phandle to system control to set configurations + for phy. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Example: + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-ld20-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + socionext,syscon = <&soc_glue>; + }; |