diff options
author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2020-07-21 19:02:33 -0700 |
---|---|---|
committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2020-07-21 19:02:33 -0700 |
commit | 9b031c86506cef9acae45e61339fcf9deaabb793 (patch) | |
tree | 9095d638ba9384f86df8d61dcf1f129c082481e1 /Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt | |
parent | 53aab92dec447f93489e07924e310d605a389dea (diff) | |
parent | 04d5ce620f794f1df69b5f1b9ad62910fea547f1 (diff) | |
download | linux-9b031c86506cef9acae45e61339fcf9deaabb793.tar.bz2 |
Merge branch 'elan-i2c' into next
Bring in update to Elan touchpad driver to support newer touchpads with
higher resolution.
Diffstat (limited to 'Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt')
-rw-r--r-- | Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt | 36 |
1 files changed, 0 insertions, 36 deletions
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt deleted file mode 100644 index 1d64b61f5171..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt +++ /dev/null @@ -1,36 +0,0 @@ -Qualcomm Quad Serial Peripheral Interface (QSPI) - -The QSPI controller allows SPI protocol communication in single, dual, or quad -wire transmission modes for read/write access to slaves such as NOR flash. - -Required properties: -- compatible: An SoC specific identifier followed by "qcom,qspi-v1", such as - "qcom,sdm845-qspi", "qcom,qspi-v1" -- reg: Should contain the base register location and length. -- interrupts: Interrupt number used by the controller. -- clocks: Should contain the core and AHB clock. -- clock-names: Should be "core" for core clock and "iface" for AHB clock. - -SPI slave nodes must be children of the SPI master node and can contain -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - qspi: spi@88df000 { - compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; - reg = <0x88df000 0x600>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "iface", "core"; - clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <&gcc GCC_QSPI_CORE_CLK>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; - }; |