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| author | Michael Ellerman <mpe@ellerman.id.au> | 2021-05-08 21:12:55 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-05-08 21:12:55 +1000 |
| commit | f96271cefe6dfd1cb04195b76f4a33e185cd7f92 (patch) | |
| tree | f290b3e7aa9c12fdc4853ce97c150c4f9abd90a3 /Documentation/devicetree/bindings/riscv/microchip.yaml | |
| parent | 32b48bf8514c28cdc89cd8069eceeb6e6cff0612 (diff) | |
| parent | dd860052c99b1e088352bdd4fb7aef46f8d2ef47 (diff) | |
| download | linux-f96271cefe6dfd1cb04195b76f4a33e185cd7f92.tar.bz2 | |
Merge branch 'master' into next
Merge master back into next, this allows us to resolve some conflicts in
arch/powerpc/Kconfig, and also re-sort the symbols under config PPC so
that they are in alphabetical order again.
Diffstat (limited to 'Documentation/devicetree/bindings/riscv/microchip.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/microchip.yaml | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml new file mode 100644 index 000000000000..3f981e897126 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/microchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC-based boards device tree bindings + +maintainers: + - Cyril Jean <Cyril.Jean@microchip.com> + - Lewis Hanly <lewis.hanly@microchip.com> + +description: + Microchip PolarFire SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - microchip,mpfs-icicle-kit + - const: microchip,mpfs + +additionalProperties: true + +... |