Merge tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of the pin control changes for the v5.9 kernel
  series:

  Core changes:

   - The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range()
     macro" was put in an immutable branch and merged into the pinctrl
     tree as well. We see these changes also here.

   - Improved debug output for pins used as GPIO.

  New drivers:

   - Ocelot Sparx5 SoC driver.

   - Intel Emmitsburg SoC subdriver.

   - Intel Tiger Lake-H SoC subdriver.

   - Qualcomm PM660 SoC subdriver.

   - Renesas SH-PFC R8A774E1 subdriver.

  Driver improvements:

   - Linear improvement and cleanups of the Intel drivers for
     Cherryview, Lynxpoint, Baytrail etc. Improved locking among other
     things.

   - Renesas SH-PFC has added support for RPC pins, groups, and
     functions to r8a77970 and r8a77980.

   - The newere Freescale (now NXP) i.MX8 pin controllers have been
     modularized. This is driven by the Google Android GKI initiative I
     think.

   - Open drain support for pins on the Qualcomm IPQ4019.

   - The Ingenic driver can handle both edges IRQ detection.

   - A big slew of documentation fixes all over the place.

   - A few irqchip template conversions by yours truly.

* tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
  dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
  pinctrl: stmfx: Use irqchip template
  pinctrl: amd: Use irqchip template
  pinctrl: mediatek: fix build for tristate changes
  pinctrl: samsung: Use bank name as irqchip name
  pinctrl: core: print gpio in pins debugfs file
  pinctrl: mediatek: add mt6779 eint support
  pinctrl: mediatek: add pinctrl support for MT6779 SoC
  pinctrl: mediatek: avoid virtual gpio trying to set reg
  pinctrl: mediatek: update pinmux definitions for mt6779
  pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API
  pinctrl: mcp23s08: Use irqchip template
  pinctrl: sx150x: Use irqchip template
  dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
  pinctrl: intel: Add Intel Emmitsburg pin controller support
  pinctl: ti: iodelay: Replace HTTP links with HTTPS ones
  Revert "gpio: omap: handle pin config bias flags"
  pinctrl: single: Use fallthrough pseudo-keyword
  pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword
  pinctrl: baytrail: Use fallthrough pseudo-keyword
  ...

1 files changed, 0 insertions, 81 deletions

diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
deleted file mode 100644
index d9b2100c98e8..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-Ingenic XBurst pin controller
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
-be used as GPIOs, multiplexed device functions are configured within the
-GPIO port configuration registers and it is typical to refer to pins using the
-naming scheme "PxN" where x is a character identifying the GPIO port with
-which the pin is associated and N is an integer from 0 to 31 identifying the
-pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
-PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
-contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
-jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
-
-
-Required properties:
---------------------
-
- - compatible: One of:
-    - "ingenic,jz4740-pinctrl"
-    - "ingenic,jz4725b-pinctrl"
-    - "ingenic,jz4760-pinctrl"
-    - "ingenic,jz4760b-pinctrl"
-    - "ingenic,jz4770-pinctrl"
-    - "ingenic,jz4780-pinctrl"
-    - "ingenic,x1000-pinctrl"
-    - "ingenic,x1000e-pinctrl"
-    - "ingenic,x1500-pinctrl"
-    - "ingenic,x1830-pinctrl"
- - reg: Address range of the pinctrl registers.
-
-
-Required properties for sub-nodes (GPIO chips):
------------------------------------------------
-
- - compatible: Must contain one of:
-    - "ingenic,jz4740-gpio"
-    - "ingenic,jz4760-gpio"
-    - "ingenic,jz4770-gpio"
-    - "ingenic,jz4780-gpio"
-    - "ingenic,x1000-gpio"
-    - "ingenic,x1830-gpio"
- - reg: The GPIO bank number.
- - interrupt-controller: Marks the device node as an interrupt controller.
- - interrupts: Interrupt specifier for the controllers interrupt.
- - #interrupt-cells: Should be 2. Refer to
-   ../interrupt-controller/interrupts.txt for more details.
- - gpio-controller: Marks the device node as a GPIO controller.
- - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
-    cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
-    GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
-   ../gpio/gpio.txt for more details.
-
-
-Example:
---------
-
-pinctrl: pin-controller@10010000 {
-	compatible = "ingenic,jz4740-pinctrl";
-	reg = <0x10010000 0x400>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	gpa: gpio@0 {
-		compatible = "ingenic,jz4740-gpio";
-		reg = <0>;
-
-		gpio-controller;
-		gpio-ranges = <&pinctrl 0 0 32>;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-
-		interrupt-parent = <&intc>;
-		interrupts = <28>;
-	};
-};