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author | Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> | 2018-12-06 18:17:33 +0530 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2018-12-13 16:03:41 +0100 |
commit | b0b41af12a1bf21a45ccfe48da194ee688170d03 (patch) | |
tree | 42e4f8de2c6c0d3ccaf25b1c1a38a4f2120abd47 /Documentation/devicetree/bindings/memory-controllers | |
parent | 651022382c7f8da46cb4872a545ee1da6d097d2a (diff) | |
download | linux-b0b41af12a1bf21a45ccfe48da194ee688170d03.tar.bz2 |
dt-bindings: memory: Add pl353 smc controller devicetree binding information
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt new file mode 100644 index 000000000000..d56615fd343a --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -0,0 +1,47 @@ +Device tree bindings for ARM PL353 static memory controller + +PL353 static memory controller supports two kinds of memory +interfaces.i.e NAND and SRAM/NOR interfaces. +The actual devices are instantiated from the child nodes of pl353 smc node. + +Required properties: +- compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell". +- reg : Controller registers map and length. +- clock-names : List of input clock names - "memclk", "apb_pclk" + (See clock bindings for details). +- clocks : Clock phandles (see clock bindings for details). +- address-cells : Must be 2. +- size-cells : Must be 1. + +Child nodes: + For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are +supported as child nodes. + +for NAND partition information please refer the below file +Documentation/devicetree/bindings/mtd/partition.txt + +Example: + smcc: memory-controller@e000e000 + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + reg = <0xe000e000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region + 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region + 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region + nand_0: flash@e1000000 { + compatible = "arm,pl353-nand-r2p1" + reg = <0 0 0x1000000>; + (...) + }; + nor0: flash@e2000000 { + compatible = "cfi-flash"; + reg = <1 0 0x2000000>; + }; + nor1: flash@e4000000 { + compatible = "cfi-flash"; + reg = <2 0 0x2000000>; + }; + }; |