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authorAlban Bedel <albeu@free.fr>2015-11-29 13:40:12 +0100
committerRob Herring <robh@kernel.org>2015-12-09 15:30:55 -0600
commit1da2f213cfaef8e3b8a93c7779d96691d226083b (patch)
tree808d552c8089fb305487ee87e4afb3816b81104a /Documentation/devicetree/bindings/memory-controllers
parentef8322427e6bb956992079e3b5fac57e65a6b5d3 (diff)
downloadlinux-1da2f213cfaef8e3b8a93c7779d96691d226083b.tar.bz2
dt-bindings: Misc fix for the ATH79 DDR controllers
Fix a few typos and reword the description of the '#qca,ddr-wb-channel-cells' property. Signed-off-by: Alban Bedel <albeu@free.fr> CC: trivial@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt8
1 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
index efe35a065714..c81af75bcd88 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
@@ -1,6 +1,6 @@
Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
-The DDR controller of the ARxxx and AR9xxx families provides an interface
+The DDR controller of the AR7xxx and AR9xxx families provides an interface
to flush the FIFO between various devices and the DDR. This is mainly used
by the IRQ controller to flush the FIFO before running the interrupt handler
of such devices.
@@ -11,9 +11,9 @@ Required properties:
"qca,[ar7100|ar7240]-ddr-controller" as fallback.
On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
fallback, otherwise "qca,ar7240-ddr-controller" should be used.
-- reg: Base address and size of the controllers memory area
-- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer
- channel
+- reg: Base address and size of the controller's memory area
+- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
+ the write buffer channel index, should be 1.
Example: