diff options
| author | Lubomir Rintel <lkundrak@v3.sk> | 2019-07-12 11:45:40 +0200 |
|---|---|---|
| committer | Lubomir Rintel <lkundrak@v3.sk> | 2019-10-17 16:18:28 +0200 |
| commit | f79a13fe5cb0395b5b7dd2caed463d9563fac0d0 (patch) | |
| tree | 068aa49379ee545c192acb6039efcfb0a7ca0cb0 /Documentation/devicetree/bindings/interrupt-controller | |
| parent | 95aecb71b84e01704a36cae8016e12e486374784 (diff) | |
| download | linux-f79a13fe5cb0395b5b7dd2caed463d9563fac0d0.tar.bz2 | |
dt-bindings: mrvl,intc: Add a MMP3 interrupt controller
Similar to MMP2 one, but has an extra range for the other core. The
muxes stay the same.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt index 608fee15a4cf..a0ed02725a9d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt @@ -1,13 +1,17 @@ * Marvell MMP Interrupt controller Required properties: -- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or - "mrvl,mmp2-mux-intc" +- compatible : Should be + "mrvl,mmp-intc" on Marvel MMP, + "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or + "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3 - reg : Address and length of the register set of the interrupt controller. If the interrupt controller is intc, address and length means the range - of the whole interrupt controller. If the interrupt controller is mux-intc, - address and length means one register. Since address of mux-intc is in the - range of intc. mux-intc is secondary interrupt controller. + of the whole interrupt controller. The "marvell,mmp3-intc" controller + also has a secondary range for the second CPU core. If the interrupt + controller is mux-intc, address and length means one register. Since + address of mux-intc is in the range of intc. mux-intc is secondary + interrupt controller. - reg-names : Name of the register set of the interrupt controller. It's only required in mux-intc interrupt controller. - interrupts : Should be the port interrupt shared by mux interrupts. It's |