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authorVinod Koul <vinod.koul@intel.com>2018-04-10 08:55:26 +0530
committerVinod Koul <vinod.koul@intel.com>2018-04-10 08:55:26 +0530
commitc21bd0a86789ed54cf7dfb948c590766484a585c (patch)
tree726a95e33d5736f3dffda829a87044302ad2a12f /Documentation/devicetree/bindings/dma
parentab2528c1b19e6e3b5a3713dfe6b054c672b4a498 (diff)
parente10734e5a0285220f46a37e8bbdfb241acebb04b (diff)
downloadlinux-c21bd0a86789ed54cf7dfb948c590766484a585c.tar.bz2
Merge branch 'topic/mtek' into for-linus
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+MediaTek High-Speed DMA Controller
+==================================
+
+This device follows the generic DMA bindings defined in dma/dma.txt.
+
+Required properties:
+
+- compatible: Must be one of
+ "mediatek,mt7622-hsdma": for MT7622 SoC
+ "mediatek,mt7623-hsdma": for MT7623 SoC
+- reg: Should contain the register's base address and length.
+- interrupts: Should contain a reference to the interrupt used by this
+ device.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "hsdma" entries.
+- power-domains: Phandle to the power domain that the device is part of
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+ hsdma: dma-controller@1b007000 {
+ compatible = "mediatek,mt7623-hsdma";
+ reg = <0 0x1b007000 0 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&ethsys CLK_ETHSYS_HSDMA>;
+ clock-names = "hsdma";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.