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author | Chris Zhong <zyw@rock-chips.com> | 2017-02-20 16:02:17 +0800 |
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committer | Sean Paul <seanpaul@chromium.org> | 2017-03-01 14:49:00 -0500 |
commit | 7fea5243d1ae912285b7caea81d756ff18f2bcaa (patch) | |
tree | 3ec7c6e6ee671af980b56bf76942ba98fbc2468b /Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | |
parent | f3b7a5b83896cb11deecab6aa30c5f53e19a83d5 (diff) | |
download | linux-7fea5243d1ae912285b7caea81d756ff18f2bcaa.tar.bz2 |
dt-bindings: add rk3399 support for dw-mipi-rockchip
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-2-git-send-email-zyw@rock-chips.com
Diffstat (limited to 'Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt')
-rw-r--r-- | Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 1753f0cc6fad..0f825686be80 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -5,10 +5,12 @@ Required properties: - #address-cells: Should be <1>. - #size-cells: Should be <0>. - compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi". + "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi". - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). - clocks, clock-names: Phandles to the controller's pll reference - clock(ref) and APB clock(pclk), as described in [1]. + clock(ref) and APB clock(pclk). For RK3399, a phy config clock + (phy_cfg) is additional required. As described in [1]. - rockchip,grf: this soc should set GRF regs to mux vopl/vopb. - ports: contain a port node with endpoint definitions as defined in [2]. For vopb,set the reg = <0> and set the reg = <1> for vopl. |