summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/clock
diff options
context:
space:
mode:
authorBorislav Petkov <bp@suse.de>2020-12-01 18:01:27 +0100
committerBorislav Petkov <bp@suse.de>2020-12-01 18:01:27 +0100
commit87314fb181f9042a226d721ab4a5579ddfca139c (patch)
treeb663e58cfe19ecf5003d4ea6e8048f6ae1925e9f /Documentation/devicetree/bindings/clock
parent2002d2951398317d0f46e64ae6d8dd58ed541c6d (diff)
parentb65054597872ce3aefbc6a666385eabdf9e288da (diff)
downloadlinux-87314fb181f9042a226d721ab4a5579ddfca139c.tar.bz2
Merge tag 'v5.10-rc6' into x86/cache
Merge -rc6 tag to pick up dependent changes. Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/hi6220-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/imx5-clock.yaml2
2 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
index ef3deb7b86ea..17ac4a3dd26a 100644
--- a/Documentation/devicetree/bindings/clock/hi6220-clock.txt
+++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
@@ -4,7 +4,7 @@ Clock control registers reside in different Hi6220 system controllers,
please refer the following document to know more about the binding rules
for these system controllers:
-Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
Required Properties:
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.yaml b/Documentation/devicetree/bindings/clock/imx5-clock.yaml
index 4d9e7c73dce9..90775c2669b8 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.yaml
@@ -57,7 +57,7 @@ examples:
};
can@53fc8000 {
- compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+ compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;