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authorGeert Uytterhoeven <geert+renesas@glider.be>2020-05-18 10:16:44 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2020-06-15 10:31:11 +0200
commitd9563c972c167e6e8b40c840d476d30af8e5f667 (patch)
tree6c6dea10584f9b9688edd9cbfc34153c1e40e9bc /Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
parentb3a9e3b9622ae10064826dccb4f7a52bd88c7407 (diff)
downloadlinux-d9563c972c167e6e8b40c840d476d30af8e5f667.tar.bz2
dt-bindings: clock: renesas: cpg: Convert to json-schema
Convert the Renesas Clock Pulse Generator (CPG) Device Tree binding documentation to json-schema, combining support for: - R-Mobile APE6 (R8A73A4) and A1 (R8A7740), - R-Car M1 (R8A7778) and H1 (R8A7779), - RZ/A1 (R7S72100), - SH-Mobile AG5 (SH73A0). Keep the example for R-Mobile A1, which shows most properties. Drop the consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200518081644.23683-1-geert+renesas@glider.be
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diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
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-* Renesas R8A73A4 Clock Pulse Generator (CPG)
-
-The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
-and several fixed ratio dividers.
-
-Required Properties:
-
- - compatible: Must be "renesas,r8a73a4-cpg-clocks"
-
- - reg: Base address and length of the memory resource used by the CPG
-
- - clocks: Reference to the parent clocks ("extal1" and "extal2")
-
- - #clock-cells: Must be 1
-
- - clock-output-names: The names of the clocks. Supported clocks are "main",
- "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
- "m1", "m2", "zx", "zs", and "hp".
-
-
-Example
--------
-
- cpg_clocks: cpg_clocks@e6150000 {
- compatible = "renesas,r8a73a4-cpg-clocks";
- reg = <0 0xe6150000 0 0x10000>;
- clocks = <&extal1_clk>, <&extal2_clk>;
- #clock-cells = <1>;
- clock-output-names = "main", "pll0", "pll1", "pll2",
- "pll2s", "pll2h", "z", "z2",
- "i", "m3", "b", "m1", "m2",
- "zx", "zs", "hp";
- };