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author | Taniya Das <tdas@codeaurora.org> | 2018-11-30 23:51:28 +0530 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2018-12-03 09:25:01 -0800 |
commit | 8ff1a156cb0b40a267fe7a2c69c06a6d566a7524 (patch) | |
tree | 2c61704e80beb4bab1cdf755950ddd2dc995854e /Documentation/devicetree/bindings/clock/qcom,lpasscc.txt | |
parent | 7898e4fef8352ef8a0d2bbd13c10fcc77c38e80e (diff) | |
download | linux-8ff1a156cb0b40a267fe7a2c69c06a6d566a7524.tar.bz2 |
dt-bindings: clock: Introduce QCOM LPASS clock bindings
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/qcom,lpasscc.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,lpasscc.txt | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file mode 100644 index 000000000000..b9e9787045b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt @@ -0,0 +1,26 @@ +Qualcomm LPASS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-lpasscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to LPASS_CC register region + Index-1 maps to LPASS_QDSP6SS register region + +Optional properties : +- reg-names : register names of LPASS domain + "cc", "qdsp6ss". + +Example: + +The below node has to be defined in the cases where the LPASS peripheral loader +would bring the subsystem out of reset. + + lpasscc: clock-controller@17014000 { + compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "cc", "qdsp6ss"; + #clock-cells = <1>; + }; |