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author | Alban Bedel <albeu@free.fr> | 2015-05-31 01:52:30 +0200 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2015-06-21 21:54:05 +0200 |
commit | 44fad3323833624941b99dafd982978e1742dd53 (patch) | |
tree | b3eec92ab1c3e0a54c89a89a757ba1d27cf20eb6 /Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | |
parent | b29e8b87d58904e3d6bacba411557b7353f8a1a0 (diff) | |
download | linux-44fad3323833624941b99dafd982978e1742dd53.tar.bz2 |
DEVICETREE: Add bindings for the ATH79 PLL controllers
Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/qca,ath79-pll.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt new file mode 100644 index 000000000000..e0fc2c11dd00 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt @@ -0,0 +1,33 @@ +Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller + +The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. + +Required Properties: +- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following + fallbacks: + - "qca,ar7100-pll" + - "qca,ar7240-pll" + - "qca,ar9130-pll" + - "qca,ar9330-pll" + - "qca,ar9340-pll" + - "qca,qca9550-pll" +- reg: Base address and size of the controllers memory area +- clock-names: Name of the input clock, has to be "ref" +- clocks: phandle of the external reference clock +- #clock-cells: has to be one + +Optional properties: +- clock-output-names: should be "cpu", "ddr", "ahb" + +Example: + + memory-controller@18050000 { + compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; + reg = <0x18050000 0x20>; + + clock-names = "ref"; + clocks = <&extosc>; + + #clock-cells = <1>; + clock-output-names = "cpu", "ddr", "ahb"; + }; |