diff options
author | Andre Przywara <andre.przywara@arm.com> | 2020-04-30 22:10:51 +0100 |
---|---|---|
committer | Rob Herring <robh@kernel.org> | 2020-05-03 11:10:41 -0500 |
commit | 04cbb87795f2c5ea35e2474039ca2b62d907b230 (patch) | |
tree | 750ae24258121a4b7ac40e44fb13bb9f0820833b /Documentation/devicetree/bindings/arm | |
parent | 16be1e40259dfe2cb06257c8ad7c80e768b9ddc4 (diff) | |
download | linux-04cbb87795f2c5ea35e2474039ca2b62d907b230.tar.bz2 |
dt-bindings: arm: Convert Calxeda L2 cache controller to json-schema
Convert the L2-ECC controller binding to DT schema format using
json-schema.
This is indented to be just used for error reporting.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
-rw-r--r-- | Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt | 15 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml | 42 |
2 files changed, 42 insertions, 15 deletions
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt deleted file mode 100644 index 94e642a33db0..000000000000 --- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Calxeda Highbank L2 cache ECC - -Properties: -- compatible : Should be "calxeda,hb-sregs-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. - -Example: - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml new file mode 100644 index 000000000000..a9fe01238a88 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank L2 cache ECC + +description: | + Binding for the Calxeda Highbank L2 cache controller ECC device. + This does not cover the actual L2 cache controller control registers, + but just the error reporting functionality. + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + compatible: + const: "calxeda,hb-sregs-l2-ecc" + + reg: + maxItems: 1 + + interrupts: + items: + - description: single bit error interrupt + - description: double bit error interrupt + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4>, <0 72 4>; + }; |