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| author | Jason Gunthorpe <jgg@nvidia.com> | 2022-12-09 15:52:17 -0400 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2022-12-09 15:52:17 -0400 |
| commit | d69e8c63fcbbf695ff7ff2c6d26efead23cfbb3a (patch) | |
| tree | 4d714ecd331233069ab718989bb017dfd934e129 /Documentation/arm64/booting.rst | |
| parent | 6cfe7bd0dfd33033683639039b5608d6534c19eb (diff) | |
| parent | 76dcd734eca23168cb008912c0f69ff408905235 (diff) | |
| download | linux-d69e8c63fcbbf695ff7ff2c6d26efead23cfbb3a.tar.bz2 | |
Merge tag 'v6.1-rc8' into rdma.git for-next
For dependencies in following patches
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'Documentation/arm64/booting.rst')
| -rw-r--r-- | Documentation/arm64/booting.rst | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 8aefa1001ae5..8c324ad638de 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -340,6 +340,14 @@ Before jumping into the kernel, the following conditions must be met: - SMCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. + - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. + + - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. + + - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. + + - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. + For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64) - If EL3 is present: |