diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-09-16 15:29:34 -0700 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-09-16 15:29:34 -0700 |
commit | 58d4fafd0b4c36838077a5d7b17df537b7226f1c (patch) | |
tree | 1b6b824c5ca4d1a5ff72219c18ee16dd23f90c4d /Documentation/admin-guide/kernel-parameters.txt | |
parent | dbcda58ad98936079c48728c12c27a2f333fb484 (diff) | |
parent | 9ce06497c2722a0f9109e4cc3ce35b7a69617886 (diff) | |
download | linux-58d4fafd0b4c36838077a5d7b17df537b7226f1c.tar.bz2 |
Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Paul Walmsley:
"Add the following new features:
- Generic CPU topology description support for DT-based platforms,
including ARM64, ARM and RISC-V.
- Sparsemem support
- Perf callchain support
- SiFive PLIC irqchip modifications, in preparation for M-mode Linux
and clean up the code base:
- Clean up chip-specific register (CSR) manipulation code, IPIs, TLB
flushing, and the RISC-V CPU-local timer code
- Kbuild cleanup from one of the Kbuild maintainers"
[ The CPU topology parts came in through the arm64 tree with a shared
branch - Linus ]
* tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
irqchip/sifive-plic: set max threshold for ignored handlers
riscv: move the TLB flush logic out of line
riscv: don't use the rdtime(h) pseudo-instructions
riscv: cleanup riscv_cpuid_to_hartid_mask
riscv: optimize send_ipi_single
riscv: cleanup send_ipi_mask
riscv: refactor the IPI code
riscv: Add support for libdw
riscv: Add support for perf registers sampling
riscv: Add perf callchain support
riscv: add arch/riscv/Kbuild
RISC-V: Implement sparsemem
riscv: Using CSR numbers to access CSRs
Diffstat (limited to 'Documentation/admin-guide/kernel-parameters.txt')
0 files changed, 0 insertions, 0 deletions