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author | Vladimir Zapolskiy <vz@mleia.com> | 2016-10-07 04:16:55 +0300 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-11-01 17:29:39 -0700 |
commit | f84d42a9cffc4ecd96f1ce3a038f841782142eb2 (patch) | |
tree | 9b5d46f343ebc2fbc874071b7bb34916144f3663 /COPYING | |
parent | 4154f61997e154a278155676fc9638c20c52ca81 (diff) | |
download | linux-f84d42a9cffc4ecd96f1ce3a038f841782142eb2.tar.bz2 |
clk: lpc32xx: add a quirk for PWM and MS clock dividers
In common clock framework CLK_DIVIDER_ONE_BASED or'ed with
CLK_DIVIDER_ALLOW_ZERO flags indicates that
1) a divider clock may be set to zero value,
2) divider's zero value is interpreted as a non-divided clock.
On the LPC32xx platform clock dividers of PWM and memory card clocks
comply with the first condition, but zero value means a gated clock,
thus it may happen that the divider value is not updated when
the clock is enabled and the clock remains gated.
The change adds one-shot quirks, which check for zero value of divider
on initialization and set it to a non-zero value, therefore in runtime
a gate clock will work as expected.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'COPYING')
0 files changed, 0 insertions, 0 deletions