diff options
| author | Michael Strauss <michael.strauss@amd.com> | 2021-09-21 13:35:19 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-19 17:17:56 -0400 |
| commit | fd8811e60db45e423b0227373fdf79447826f0ca (patch) | |
| tree | 820267824d4c109e63e2f92d81091b718d79dbb8 | |
| parent | 05692bb02abd63959fde2108dbe80dd5082e4f89 (diff) | |
| download | linux-fd8811e60db45e423b0227373fdf79447826f0ca.tar.bz2 | |
drm/amd/display: Clean Up VPG Low Mem Power
[WHAT]
One of the current VPG power on calls is unnecessary
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 13 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 |
3 files changed, 13 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f9876e429f26..8be04be19124 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -71,8 +71,6 @@ #include "dmub/dmub_srv.h" -#include "dcn30/dcn30_vpg.h" - #include "i2caux_interface.h" #include "dce/dmub_hw_lock_mgr.h" @@ -2674,9 +2672,6 @@ static void commit_planes_do_stream_update(struct dc *dc, enum surface_update_type update_type, struct dc_state *context) { -#if defined(CONFIG_DRM_AMD_DC_DCN) - struct vpg *vpg; -#endif int j; // Stream updates @@ -2697,11 +2692,6 @@ static void commit_planes_do_stream_update(struct dc *dc, stream_update->vrr_infopacket || stream_update->vsc_infopacket || stream_update->vsp_infopacket) { -#if defined(CONFIG_DRM_AMD_DC_DCN) - vpg = pipe_ctx->stream_res.stream_enc->vpg; - if (vpg && vpg->funcs->vpg_poweron) - vpg->funcs->vpg_poweron(vpg); -#endif resource_build_info_frame(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c index 18e33ef3d217..968b8825dec7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -49,6 +49,7 @@ #include "inc/link_dpcd.h" #include "dcn10/dcn10_hw_sequencer.h" #include "inc/link_enc_cfg.h" +#include "dcn30/dcn30_vpg.h" #define DC_LOGGER_INIT(logger) @@ -126,6 +127,18 @@ void dcn31_init_hw(struct dc *dc) REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); } +#if defined(CONFIG_DRM_AMD_DC_DCN) + if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { + // Power down VPGs + for (i = 0; i < dc->res_pool->stream_enc_count; i++) + dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); +#if defined(CONFIG_DRM_AMD_DC_DP2_0) + for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) + dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); +#endif + } +#endif + if (dc->ctx->dc_bios->fw_info_valid) { res_pool->ref_clocks.xtalin_clock_inKhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c index 7cb7604a35eb..20b4202bda13 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c @@ -1312,10 +1312,6 @@ static struct vpg *dcn31_vpg_create( &vpg_shift, &vpg_mask); - // Will re-enable hw block when we enable stream - // Check for enabled stream before powering down? - vpg31_powerdown(&vpg31->base); - return &vpg31->base; } |