diff options
| author | Chris Brandt <chris.brandt@renesas.com> | 2017-02-14 11:08:05 -0500 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-02-16 10:36:05 -0800 |
| commit | f59de563358eb9351b7f8f0ba2d3be2ebb70b93d (patch) | |
| tree | 0e008be6cd260a00e1d49f024345af0a1d4abfa9 | |
| parent | 6ff8ec98e12f984b9d62e43f83b0a3c44e2bdc12 (diff) | |
| download | linux-f59de563358eb9351b7f8f0ba2d3be2ebb70b93d.tar.bz2 | |
clk: renesas: mstp: ensure register writes complete
When there is no status bit, it is possible for the clock enable/disable
operation to have not completed by the time the driver code resumes
execution. This is due to the fact that write operations are sometimes
queued and delayed internally. Doing a read ensures the write operations
has completed.
Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| -rw-r--r-- | drivers/clk/renesas/clk-mstp.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c index 3ce819c26077..4067216bf31f 100644 --- a/drivers/clk/renesas/clk-mstp.c +++ b/drivers/clk/renesas/clk-mstp.c @@ -91,6 +91,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) value |= bitmask; cpg_mstp_write(group, value, group->smstpcr); + if (!group->mstpsr) { + /* dummy read to ensure write has completed */ + cpg_mstp_read(group, group->smstpcr); + barrier_data(group->smstpcr); + } + spin_unlock_irqrestore(&group->lock, flags); if (!enable || !group->mstpsr) |