diff options
| author | Wayne Boyer <wayne.boyer@intel.com> | 2022-10-31 06:15:09 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-11-01 14:29:39 -0700 |
| commit | ea9c6215ac6ba8db51d0af6cce71b6aa959364c2 (patch) | |
| tree | 0f768eaacf7489fac26f5764a58de8c02bbd2c66 | |
| parent | 3096ae43cc815835cbaa846ae54e18cb92307730 (diff) | |
| download | linux-ea9c6215ac6ba8db51d0af6cce71b6aa959364c2.tar.bz2 | |
drm/i915/dg2: Introduce Wa_18017747507
WA 18017747507 applies to all DG2 skus.
BSpec: 56035, 46121, 68173
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221031131509.3411195-1-wayne.boyer@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 1b901970cfa4..dfbf093ec562 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -498,6 +498,9 @@ #define VF_PREEMPTION _MMIO(0x83a4) #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) +#define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4) +#define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) + #define GEN8_RC6_CTX_INFO _MMIO(0x8504) #define XEHP_SQCM MCR_REG(0x8724) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f87d4bde761b..8c98567f7a78 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2975,6 +2975,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * Wa_22015475538:dg2 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18017747507:dg2 */ + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); } } |