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| author | Bjorn Andersson <quic_bjorande@quicinc.com> | 2022-11-10 19:25:12 -0800 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2022-12-06 11:05:28 -0600 |
| commit | e4f68d6c32aec8f3c7cdb07d18278e9a068a7eb0 (patch) | |
| tree | 8d689dd4d88616c5941eefd8ff95daa8dea83552 | |
| parent | a0289a1040a557428a65d099dfdebe80f1a0d0eb (diff) | |
| download | linux-e4f68d6c32aec8f3c7cdb07d18278e9a068a7eb0.tar.bz2 | |
arm64: dts: qcom: sc8280xp: Add epss_l3 node
Add a device node for the EPSS L3 frequency domain.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-8-quic_bjorande@quicinc.com
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0facb77ec91a..2337ddfea896 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2260,6 +2260,16 @@ }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; + reg = <0 0x18590000 0 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, |