summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJack Xiao <Jack.Xiao@amd.com>2019-05-06 16:35:41 +0800
committerAlex Deucher <alexander.deucher@amd.com>2019-06-21 18:59:29 -0500
commite17a512a18c1f1dece8c3d4f9685c581052d3191 (patch)
treedac01b476cbef7eb72ee66f3bb3eb09793b2c3d8
parent2a8bfa139a4515cd020c7a5be1e1e45d5d116352 (diff)
downloadlinux-e17a512a18c1f1dece8c3d4f9685c581052d3191.tar.bz2
drm/amdgpu: RLC must be disabled after SMU when S3 on navi
SMU requires to interact with RLC when disable all features, so RLC shouldn't be disabled ahead of SMU. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/amdgpu_smu.c4
2 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f9ad98889c7d..80b100caf628 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1573,8 +1573,6 @@ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
-
- gfx_v10_0_enable_gui_idle_interrupt(adev, false);
}
static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
@@ -3607,7 +3605,7 @@ static int gfx_v10_0_hw_fini(void *handle)
return 0;
}
gfx_v10_0_cp_enable(adev, false);
- gfx_v10_0_rlc_stop(adev);
+ gfx_v10_0_enable_gui_idle_interrupt(adev, false);
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 9e0b439b41ca..30dae7ca19c4 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -943,6 +943,10 @@ static int smu_suspend(void *handle)
smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
+ if (adev->asic_type >= CHIP_NAVI10 &&
+ adev->gfx.rlc.funcs->stop)
+ adev->gfx.rlc.funcs->stop(adev);
+
return 0;
}