diff options
| author | Zhao Qiang <qiang.zhao@nxp.com> | 2016-05-17 10:39:02 +0800 |
|---|---|---|
| committer | Scott Wood <oss@buserror.net> | 2016-07-09 01:12:04 -0500 |
| commit | df02087d271ca3568ce0b8abd334305ecdda9060 (patch) | |
| tree | cb50db8d1d021768c0dbca36f34f371650d8e8e3 | |
| parent | b7a7085204f42a2b0095396287341ad313c47444 (diff) | |
| download | linux-df02087d271ca3568ce0b8abd334305ecdda9060.tar.bz2 | |
T104xRDB: Add qe node to t104xrdb
add qe node to t104xrdb.dtsi
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: Scott Wood <oss@buserror.net>
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi index 7c4afdb44b46..5fdddbd2a62b 100644 --- a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi +++ b/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi @@ -222,4 +222,42 @@ 0 0x00010000>; }; }; + + qe: qe@ffe140000 { + ranges = <0x0 0xf 0xfe140000 0x40000>; + reg = <0xf 0xfe140000 0 0x480>; + brg-frequency = <0>; + bus-frequency = <0>; + + si1: si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + + siram1: siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + + ucc_hdlc: ucc@2000 { + compatible = "fsl,ucc-hdlc"; + rx-clock-name = "clk8"; + tx-clock-name = "clk9"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot-mask = <0xfffffffe>; + fsl,rx-timeslot-mask = <0xfffffffe>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-id = <0>; + fsl,siram-entry-id = <0>; + fsl,tdm-interface; + }; + + ucc_serial: ucc@2200 { + compatible = "fsl,t1040-ucc-uart"; + port-number = <0>; + rx-clock-name = "brg2"; + tx-clock-name = "brg2"; + }; + }; }; |