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authorStephen Boyd <sboyd@codeaurora.org>2017-01-26 16:10:57 -0800
committerStephen Boyd <sboyd@codeaurora.org>2017-01-26 16:10:57 -0800
commitde9b5a24047d50490ff58428bd1dc8bc4b63a225 (patch)
treef1eb3a252979c6ce66ac1561ef7916956106d887
parent3d21a4b6462aa2578192705b7b1eb4d40054d531 (diff)
parent55921ce27695325e7bab667ccc7e4ada81a74f02 (diff)
downloadlinux-de9b5a24047d50490ff58428bd1dc8bc4b63a225.tar.bz2
Merge branch 'clk-ux500' into clk-next
* clk-ux500: clk: ux500: Convert ABx500 clocks to use OF probing clk: ux500: Add device tree bindings for ABx500 clocks clk: ux500: move AB8500 sysclk over to PRCMU clk driver
-rw-r--r--Documentation/devicetree/bindings/clock/stericsson,abx500.txt20
-rw-r--r--drivers/clk/ux500/abx500-clk.c44
-rw-r--r--drivers/clk/ux500/u8500_of_clk.c3
-rw-r--r--include/dt-bindings/clock/ste-ab8500.h11
4 files changed, 60 insertions, 18 deletions
diff --git a/Documentation/devicetree/bindings/clock/stericsson,abx500.txt b/Documentation/devicetree/bindings/clock/stericsson,abx500.txt
new file mode 100644
index 000000000000..dbaa886b223e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/stericsson,abx500.txt
@@ -0,0 +1,20 @@
+Clock bindings for ST-Ericsson ABx500 clocks
+
+Required properties :
+- compatible : shall contain the following:
+ "stericsson,ab8500-clk"
+- #clock-cells should be <1>
+
+The ABx500 clocks need to be placed as a subnode of an AB8500
+device node, see mfd/ab8500.txt
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/ste-ab8500.h header and can be used in device
+tree sources.
+
+Example:
+
+clock-controller {
+ compatible = "stericsson,ab8500-clk";
+ #clock-cells = <1>;
+};
diff --git a/drivers/clk/ux500/abx500-clk.c b/drivers/clk/ux500/abx500-clk.c
index a07c31e6f26d..2257d12ba988 100644
--- a/drivers/clk/ux500/abx500-clk.c
+++ b/drivers/clk/ux500/abx500-clk.c
@@ -10,20 +10,26 @@
#include <linux/err.h>
#include <linux/module.h>
#include <linux/device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/mfd/abx500/ab8500-sysctrl.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <dt-bindings/clock/ste-ab8500.h>
#include "clk.h"
+#define AB8500_NUM_CLKS 6
+
+static struct clk *ab8500_clks[AB8500_NUM_CLKS];
+static struct clk_onecell_data ab8500_clk_data;
+
/* Clock definitions for ab8500 */
static int ab8500_reg_clks(struct device *dev)
{
int ret;
struct clk *clk;
-
+ struct device_node *np = dev->of_node;
const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"};
u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1};
u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK};
@@ -32,55 +38,52 @@ static int ab8500_reg_clks(struct device *dev)
(1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT)
};
- dev_info(dev, "register clocks for ab850x\n");
-
/* Enable SWAT */
ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE);
if (ret)
return ret;
- /* ab8500_sysclk */
- clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
- clk_register_clkdev(clk, "sysclk", "ab8500-usb.0");
- clk_register_clkdev(clk, "sysclk", "ab-iddet.0");
- clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0");
- clk_register_clkdev(clk, "sysclk", "shrm_bus");
-
/* ab8500_sysclk2 */
clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ,
AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0);
- clk_register_clkdev(clk, "sysclk", "0-0070");
+ ab8500_clks[AB8500_SYSCLK_BUF2] = clk;
/* ab8500_sysclk3 */
clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk",
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ,
AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0);
- clk_register_clkdev(clk, "sysclk", "cg1960_core.0");
+ ab8500_clks[AB8500_SYSCLK_BUF3] = clk;
/* ab8500_sysclk4 */
clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk",
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ,
AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0);
+ ab8500_clks[AB8500_SYSCLK_BUF4] = clk;
/* ab_ulpclk */
clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL,
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
38400000, 9000, 0);
- clk_register_clkdev(clk, "ulpclk", "snd-soc-mop500.0");
+ ab8500_clks[AB8500_SYSCLK_ULP] = clk;
/* ab8500_intclk */
clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2,
intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0);
- clk_register_clkdev(clk, "intclk", "snd-soc-mop500.0");
- clk_register_clkdev(clk, NULL, "ab8500-pwm.1");
+ ab8500_clks[AB8500_SYSCLK_INT] = clk;
/* ab8500_audioclk */
clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk",
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA,
AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0);
- clk_register_clkdev(clk, "audioclk", "ab8500-codec.0");
+ ab8500_clks[AB8500_SYSCLK_AUDIO] = clk;
+
+ ab8500_clk_data.clks = ab8500_clks;
+ ab8500_clk_data.clk_num = ARRAY_SIZE(ab8500_clks);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &ab8500_clk_data);
+
+ dev_info(dev, "registered clocks for ab850x\n");
return 0;
}
@@ -116,9 +119,15 @@ static int abx500_clk_probe(struct platform_device *pdev)
return ret;
}
+static const struct of_device_id abx500_clk_match[] = {
+ { .compatible = "stericsson,ab8500-clk", },
+ {}
+};
+
static struct platform_driver abx500_clk_driver = {
.driver = {
.name = "abx500-clk",
+ .of_match_table = abx500_clk_match,
},
.probe = abx500_clk_probe,
};
@@ -127,7 +136,6 @@ static int __init abx500_clk_init(void)
{
return platform_driver_register(&abx500_clk_driver);
}
-
arch_initcall(abx500_clk_init);
MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org");
diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c
index e960d686d9db..d5888591e1a9 100644
--- a/drivers/clk/ux500/u8500_of_clk.c
+++ b/drivers/clk/ux500/u8500_of_clk.c
@@ -206,6 +206,9 @@ static void u8500_clk_init(struct device_node *np)
clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
prcmu_clk[PRCMU_TIMCLK] = clk;
+ clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
+ prcmu_clk[PRCMU_SYSCLK] = clk;
+
clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
100000000, CLK_SET_RATE_GATE);
prcmu_clk[PRCMU_SDMMCCLK] = clk;
diff --git a/include/dt-bindings/clock/ste-ab8500.h b/include/dt-bindings/clock/ste-ab8500.h
new file mode 100644
index 000000000000..6731f1f00a84
--- /dev/null
+++ b/include/dt-bindings/clock/ste-ab8500.h
@@ -0,0 +1,11 @@
+#ifndef __STE_CLK_AB8500_H__
+#define __STE_CLK_AB8500_H__
+
+#define AB8500_SYSCLK_BUF2 0
+#define AB8500_SYSCLK_BUF3 1
+#define AB8500_SYSCLK_BUF4 2
+#define AB8500_SYSCLK_ULP 3
+#define AB8500_SYSCLK_INT 4
+#define AB8500_SYSCLK_AUDIO 5
+
+#endif