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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-07-27 10:10:58 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-07-27 10:10:58 +0100
commitdaf93dd55c48b65ab2f1907e0fc5ef994896c787 (patch)
tree38465ea53d1861c7583193b7bb031b20bf05c453
parent6cab48602996cdbcb277375a8107d53e21e8c9b9 (diff)
downloadlinux-daf93dd55c48b65ab2f1907e0fc5ef994896c787.tar.bz2
[ARM] fix VIPT/VIVT macro optimisations, add comments
cacheflush.h was doing: ... VIVT only stuff ... VIPT only stuff ... VIVT or VIPT stuff which is clearly bogus - we would only ever use the "VIVT or VIPT" case when both VIVT and VIPT are not selected. Fix this. Add comments to each case, including noting the impossibility of correctly detecting the cache type of ARM926 and ARMv6 cores from the cache type register in the "VIVT or VIPT" case. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--include/asm-arm/cacheflush.h17
1 files changed, 13 insertions, 4 deletions
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 03cf1ee977b7..e68a1cbcc852 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -459,15 +459,19 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
#define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
-
+/*
+ * VIVT caches only
+ */
#define cache_is_vivt() 1
#define cache_is_vipt() 0
#define cache_is_vipt_nonaliasing() 0
#define cache_is_vipt_aliasing() 0
#define icache_is_vivt_asid_tagged() 0
-#elif defined(CONFIG_CPU_CACHE_VIPT)
-
+#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
+/*
+ * VIPT caches only
+ */
#define cache_is_vivt() 0
#define cache_is_vipt() 1
#define cache_is_vipt_nonaliasing() \
@@ -489,7 +493,12 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
})
#else
-
+/*
+ * VIVT or VIPT caches. Note that this is unreliable since ARM926
+ * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
+ * There's no way to tell from the CacheType register what type (!)
+ * the cache is.
+ */
#define cache_is_vivt() \
({ \
unsigned int __val = read_cpuid(CPUID_CACHETYPE); \