diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-06-20 18:14:22 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2020-06-24 12:14:30 +0200 |
| commit | d4db5721f3c847df43b967d9f02994b15e4a48e6 (patch) | |
| tree | 191118bd24cc0a467a6407b01c4eb97d20e4d53c | |
| parent | 2f1efa5340eff9af36c9a7347bb97abd726128a0 (diff) | |
| download | linux-d4db5721f3c847df43b967d9f02994b15e4a48e6.tar.bz2 | |
clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't
know the relation between this clock and RGMII Ethernet. It turns out
that fclk_div2 is used as "timing adjustment clock" to generate the RX
delay on the MAC side - which was enabled by u-boot on Odriod-C1. When
using the RX delay on the PHY side or not using a RX delay at all then
this clock can be disabled.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200620161422.24114-1-martin.blumenstingl@googlemail.com
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index edc09d050ecf..3d826711c820 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -293,13 +293,6 @@ static struct clk_regmap meson8b_fclk_div2 = { &meson8b_fclk_div2_div.hw }, .num_parents = 1, - /* - * FIXME: Ethernet with a RGMII PHYs is not working if - * fclk_div2 is disabled. it is currently unclear why this - * is. keep it enabled until the Ethernet driver knows how - * to manage this clock. - */ - .flags = CLK_IS_CRITICAL, }, }; |