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authorStephane Eranian <eranian@google.com>2022-08-17 22:46:13 -0700
committerPeter Zijlstra <peterz@infradead.org>2022-08-19 19:47:31 +0200
commitd4bdb0bebc5ba3299d74f123c782d99cd4e25c49 (patch)
treeb008b58262d83658571f1d51838c019e501324dc
parent7d3598868aaee05eb738d1c3115616b867e7530a (diff)
downloadlinux-d4bdb0bebc5ba3299d74f123c782d99cd4e25c49.tar.bz2
perf/x86/intel/ds: Fix precise store latency handling
With the existing code in store_latency_data(), the memory operation (mem_op) returned to the user is always OP_LOAD where in fact, it should be OP_STORE. This comes from the fact that the function is simply grabbing the information from a data source map which covers only load accesses. Intel 12th gen CPU offers precise store sampling that captures both the data source and latency. Therefore it can use the data source mapping table but must override the memory operation to reflect stores instead of loads. Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids") Signed-off-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20220818054613.1548130-1-eranian@google.com
-rw-r--r--arch/x86/events/intel/ds.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index ac6dd4c96dbc..e5b587499122 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -291,6 +291,7 @@ static u64 load_latency_data(struct perf_event *event, u64 status)
static u64 store_latency_data(struct perf_event *event, u64 status)
{
union intel_x86_pebs_dse dse;
+ union perf_mem_data_src src;
u64 val;
dse.val = status;
@@ -304,7 +305,14 @@ static u64 store_latency_data(struct perf_event *event, u64 status)
val |= P(BLK, NA);
- return val;
+ /*
+ * the pebs_data_source table is only for loads
+ * so override the mem_op to say STORE instead
+ */
+ src.val = val;
+ src.mem_op = P(OP,STORE);
+
+ return src.val;
}
struct pebs_record_core {