diff options
| author | Yakir Yang <ykk@rock-chips.com> | 2016-06-29 17:15:05 +0800 |
|---|---|---|
| committer | Yakir Yang <ykk@rock-chips.com> | 2016-07-05 09:16:38 +0800 |
| commit | cb5571fcf809860c455f6b62bb5252f277b52e83 (patch) | |
| tree | ce79819098ac319e19fceb05c5d6db9484221e20 | |
| parent | d9c900b0270a18101403cf5e95c1639fccd43a9f (diff) | |
| download | linux-cb5571fcf809860c455f6b62bb5252f277b52e83.tar.bz2 | |
drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1
There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").
The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
| -rw-r--r-- | drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h index 337912b0aeab..88d56ad5c010 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -163,8 +163,8 @@ #define HSYNC_POLARITY_CFG (0x1 << 0) /* ANALOGIX_DP_PLL_REG_1 */ -#define REF_CLK_24M (0x1 << 1) -#define REF_CLK_27M (0x0 << 1) +#define REF_CLK_24M (0x1 << 0) +#define REF_CLK_27M (0x0 << 0) /* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) |