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authorJohn Clements <john.clements@amd.com>2020-07-17 14:13:50 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-07-21 15:37:39 -0400
commitc652923afa7c8fef2aee42142e9663c0e69f367d (patch)
tree7e40f9d51dd37f518a5a0b911b82b7617710617b
parentcff5f790193c0ab262a59e80f6024c932f5dcc9f (diff)
downloadlinux-c652923afa7c8fef2aee42142e9663c0e69f367d.tar.bz2
drm/amdgpu: enable xgmi support for sienna cichlid
set xgmi support flag suring nv ip init sequence Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nv.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 479991b71295..ea69ae76773e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -446,6 +446,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
adev->nbio.funcs = &nbio_v2_3_funcs;
adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ adev->gmc.xgmi.supported = true;
+
/* Set IP register base before any HW register access */
r = nv_reg_base_init(adev);
if (r)