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| author | Nagarjuna Kristam <nkristam@nvidia.com> | 2020-04-16 13:04:18 +0530 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-05-13 12:59:42 +0200 |
| commit | bc8788b2f3a0c1adf1bdcde12bb5b5642e3e043e (patch) | |
| tree | 449072bc1ce98b56d71b7b986461d38495954103 | |
| parent | d3cd7d02e7133e2c0809c25d5321af21af695da4 (diff) | |
| download | linux-bc8788b2f3a0c1adf1bdcde12bb5b5642e3e043e.tar.bz2 | |
arm64: tegra: Add XUDC node on Tegra194
Tegra194 has one XUSB device mode controller which can be operated in HS
and SS modes. Add a DT node for this XUSB device mode controller.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f4ede86e32b4..e1ae01c2d039 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -644,6 +644,24 @@ }; }; + usb@3550000 { + compatible = "nvidia,tegra194-xudc"; + reg = <0x03550000 0x8000>, + <0x03558000 0x1000>; + reg-names = "base", "fpci"; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA194_CLK_XUSB_SS>, + <&bpmp TEGRA194_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; + usb@3610000 { compatible = "nvidia,tegra194-xusb"; reg = <0x03610000 0x40000>, |