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authorMichael J. Ruhl <michael.j.ruhl@intel.com>2018-09-10 07:54:04 -0700
committerJason Gunthorpe <jgg@mellanox.com>2018-09-11 11:33:13 -0600
commitb53ae6bc7e397930ff20221d1a5976677e0dc85b (patch)
treea860c7319e42e2973ca6ce7eddffc12b3236c14a
parent2bf4b33f83dfe521c4c7c407b6b150aeec04d69c (diff)
downloadlinux-b53ae6bc7e397930ff20221d1a5976677e0dc85b.tar.bz2
IB/hfi1: set_intr_bits uses incorrect source for register modification
HFI IRQ enable bits are not being set correctly. Send context error and DC IRQs are not being enabled correctly. In addition, send context error IRQs are not being delivered. Because of this, send context errors are not being handled correctly when they occur. When setting the IRQ bits, if an IRQ range is used, and the last bit is on a register boundary (bit 63), the calculated index for the final register modification is incorrect (index + 1 vs. index). The incorrect index calculation causes incorrect IRQ bits to be set. In this case the send context error IRQ is NOT enabled. Fix by using the 'last' value rather than the counted 'src' value to determine the final index to use. This satisfies all cases. Fixes: a2f7bbdc2dba ("IB/hfi1: Rework the IRQ API to be more flexible") Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
-rw-r--r--drivers/infiniband/hw/hfi1/chip.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c
index ef433fdb2411..290c3b5b22f3 100644
--- a/drivers/infiniband/hw/hfi1/chip.c
+++ b/drivers/infiniband/hw/hfi1/chip.c
@@ -13012,7 +13012,7 @@ int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set)
}
bits |= BIT_ULL(bit);
}
- read_mod_write(dd, src, bits, set);
+ read_mod_write(dd, last, bits, set);
return 0;
}