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| author | Will Deacon <will@kernel.org> | 2021-06-24 13:37:47 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2021-06-24 13:37:47 +0100 |
| commit | aeb3e82e432350234cd6803daf3057832d5e1178 (patch) | |
| tree | 11c398c654c49de865a02e89b6cab7f9ab4b1035 | |
| parent | eea3e2dec4c856677333fee7e8d56547cbd99121 (diff) | |
| parent | ca940790d2ddc91e976f1e9e685052a54a1c50cf (diff) | |
| download | linux-aeb3e82e432350234cd6803daf3057832d5e1178.tar.bz2 | |
Merge branch 'for-next/docs' into for-next/core
Update booting requirements for the FEAT_HCX feature, added to v8.7 of
the architecture.
* for-next/docs:
arm64: Document requirement for access to FEAT_HCX
| -rw-r--r-- | Documentation/arm64/booting.rst | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 18b8cc1bf32c..a9192e7a231b 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -277,6 +277,12 @@ Before jumping into the kernel, the following conditions must be met: - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.HXEn (bit 38) must be initialised to 0b1. + For CPUs with Advanced SIMD and floating point support: - If EL3 is present: |