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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-01-30 17:51:10 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-01-31 09:00:08 +0200 |
| commit | ad3e7b824c185125f281d56a9e8f614effcdae91 (patch) | |
| tree | 7f4c74dea7dfb182bea21cc10c332f6313041cf0 | |
| parent | e4c0d5314dede34ac48257cbdd4b3a046b2415df (diff) | |
| download | linux-ad3e7b824c185125f281d56a9e8f614effcdae91.tar.bz2 | |
drm/i915: Don't use the second dbuf slice on icl
The code managing the dbuf slices is borked and needs some
real work to fix. In the meantime let's just stop using the
second slice.
v2: Drop the change to intel_enabled_dbuf_slices_num() (Mahesh)
Cc: Mahesh Kumar <mahesh1.sh.kumar@gmail.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190130155110.12918-1-ville.syrjala@linux.intel.com
Reviewed-by: Mahesh Kumar <mahesh1.sh.kumar@gmail.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 53b706154c94..ed9786241307 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3822,8 +3822,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv, /* * 12GB/s is maximum BW supported by single DBuf slice. + * + * FIXME dbuf slice code is broken: + * - must wait for planes to stop using the slice before powering it off + * - plane straddling both slices is illegal in multi-pipe scenarios + * - should validate we stay within the hw bandwidth limits */ - if (num_active > 1 || total_data_bw >= GBps(12)) { + if (0 && (num_active > 1 || total_data_bw >= GBps(12))) { ddb->enabled_slices = 2; } else { ddb->enabled_slices = 1; |