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| author | Stephen Boyd <sboyd@kernel.org> | 2022-09-28 16:07:09 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-09-28 16:07:09 -0700 |
| commit | acb84a167f14ae7d51475379ca1ff2f7bb36e2b6 (patch) | |
| tree | 928afa94409bd2c9c2bdc27e43e198df0367655f | |
| parent | 9e1ab1fef1ec4542fea79bb02ace412e70aa163c (diff) | |
| parent | e46a1a9943c0e84f439b971d6ce03f87e3d67441 (diff) | |
| download | linux-acb84a167f14ae7d51475379ca1ff2f7bb36e2b6.tar.bz2 | |
Merge tag 'renesas-clk-for-v6.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull some more Renesas clk driver updates from Geert Uytterhoeven:
- Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car
V4H
* tag 'renesas-clk-for-v6.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779g0: Add EtherAVB clocks
clk: renesas: r8a779g0: Add PFC/GPIO clocks
clk: renesas: r8a779g0: Add I2C clocks
clk: renesas: r8a779g0: Add watchdog clock
| -rw-r--r-- | drivers/clk/renesas/r8a779g0-cpg-mssr.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 3fc4233b1ead..9641122133b5 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -150,10 +150,24 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { + DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC), + DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC), + DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC), DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER), DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER), DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER), DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER), + DEF_MOD("i2c0", 518, R8A779G0_CLK_S0D6_PER), + DEF_MOD("i2c1", 519, R8A779G0_CLK_S0D6_PER), + DEF_MOD("i2c2", 520, R8A779G0_CLK_S0D6_PER), + DEF_MOD("i2c3", 521, R8A779G0_CLK_S0D6_PER), + DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER), + DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER), + DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R), + DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M), + DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M), + DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M), + DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M), }; /* |