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| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2021-06-07 14:01:49 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-06-09 14:19:21 +0200 |
| commit | aa6c32f9fe0de12f685d441faf9a73dd277af209 (patch) | |
| tree | 4eab31eabc6e6f5e553cbaeed3cae8383b5b8ba8 | |
| parent | a3bb1d050e436e5ad301491315ea42c9ac0821c5 (diff) | |
| download | linux-aa6c32f9fe0de12f685d441faf9a73dd277af209.tar.bz2 | |
staging: mt7621-pci: remove 'RALINK_PCI_BAR0SETUP_ADDR' definition
Instead of define RALINK_PCI_BAR0SETUP_ADDR just use standard
pci defnition for this which is 'PCI_BASE_ADDRESS_0'.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210607120153.24989-3-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index c14fc48e74fc..b83c338a2e3d 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -47,7 +47,6 @@ #define MT7621_PCIE_OFFSET 0x2000 #define MT7621_NEXT_PORT 0x1000 -#define RALINK_PCI_BAR0SETUP_ADDR 0x0010 #define RALINK_PCI_ID 0x0030 #define RALINK_PCI_CLASS 0x0034 #define RALINK_PCI_SUBID 0x0038 @@ -494,7 +493,7 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) /* map 2G DDR region */ pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, - offset + RALINK_PCI_BAR0SETUP_ADDR); + offset + PCI_BASE_ADDRESS_0); /* configure class code and revision ID */ pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID, |