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| author | Michel Pollet <michel.pollet@bp.renesas.com> | 2018-06-28 09:17:12 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-06-28 14:07:21 +0200 |
| commit | a7eaad7f7517ba7cdabfeb28fa05bae4e70b4b5a (patch) | |
| tree | e7a3f4406feff65c1314975070c185da72e15f6e | |
| parent | 403cc7037f3858c3029fdf7629960516c7d3aced (diff) | |
| download | linux-a7eaad7f7517ba7cdabfeb28fa05bae4e70b4b5a.tar.bz2 | |
dt-bindings: cpu: Add Renesas R9A06G032 SMP enable method.
Add a special enable method for second CA7 of the R9A06G032
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | Documentation/devicetree/bindings/arm/cpus.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 29e1dc5d506d..b395d1071240 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -219,6 +219,7 @@ described below. "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" "renesas,apmu" + "renesas,r9a06g032-smp" "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" |