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author | Marek Szyprowski <m.szyprowski@samsung.com> | 2020-11-13 18:01:37 +0100 |
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committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-11-23 09:51:02 +0000 |
commit | a7b4dba9a71d64e07fbc9802bbc1eaad5494f071 (patch) | |
tree | 2b2c1b2230d654e62e0e6fe75979a84f5d4fe839 | |
parent | eea23e4a00d479eea6d15a78b79f0c58e8ee4467 (diff) | |
download | linux-a7b4dba9a71d64e07fbc9802bbc1eaad5494f071.tar.bz2 |
dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding
Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433
variant). Based on the text dt-binding posted by Jaehoon Chung.
Link: https://lore.kernel.org/r/20201113170139.29956-4-m.szyprowski@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
-rw-r--r-- | Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml new file mode 100644 index 000000000000..ac0af40be52d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe PHY Device Tree Bindings + +maintainers: + - Marek Szyprowski <m.szyprowski@samsung.com> + - Jaehoon Chung <jh80.chung@samsung.com> + +properties: + "#phy-cells": + const: 0 + + compatible: + const: samsung,exynos5433-pcie-phy + + reg: + maxItems: 1 + + samsung,pmu-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for PMU system controller interface, used to + control PMU registers bits for PCIe PHY + + samsung,fsys-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for FSYS sysreg interface, used to control + sysreg registers bits for PCIe PHY + +required: + - "#phy-cells" + - compatible + - reg + - samsung,pmu-syscon + - samsung,fsys-sysreg + +additionalProperties: false + +examples: + - | + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + }; +... |