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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-12 11:35:06 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-10-16 11:36:18 +0200 |
| commit | a7869a5bc82682ac31452e178b4b3e9f8b48e7df (patch) | |
| tree | 52d48878bc2ec4d424dc58bbc40d6fc853eb3424 | |
| parent | 7ee06c8a0b3a1fad3d9660da00e895aaf784fdee (diff) | |
| download | linux-a7869a5bc82682ac31452e178b4b3e9f8b48e7df.tar.bz2 | |
ARM: dts: r8a73a4: Add clock for CA15 CPU0 core
Improve hardware description by adding a clocks property to the device
node corresponding to the primary CA15 CPU core, which is for now the
only one described.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm/boot/dts/r8a73a4.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 310222634570..dd4d09712a2a 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -27,6 +27,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; clock-frequency = <1500000000>; power-domains = <&pd_a2sl>; next-level-cache = <&L2_CA15>; |