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author | Bhupesh Sharma <bhupesh.sharma@freescale.com> | 2015-10-24 01:01:53 +0530 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2015-10-23 22:24:45 +0200 |
commit | a2cce7a9f1b8cc3d4edce106fb971529f1d4d9ce (patch) | |
tree | 23c05167281d7fffa589b31c7fcaca770b2f49b4 | |
parent | cc56a128a5c0875196c7518cf8147e16384b2329 (diff) | |
download | linux-a2cce7a9f1b8cc3d4edce106fb971529f1d4d9ce.tar.bz2 |
Documentation/dts: Move FSL board-specific bindings out of /powerpc
Since the same board components can be used across ARM and PPC board families,
this patch moves the FSL board-specific bindings out of bindings/powerpci.
While at it, this patch also adds the bindings for QIXIS FPGA controller
found on FSL LS2080A boards. These boards have an on-board FPGA/CPLD
connected to the IFC controller.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r-- | Documentation/devicetree/bindings/board/fsl-board.txt (renamed from Documentation/devicetree/bindings/powerpc/fsl/board.txt) | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/board/fsl-board.txt index cff38bdbc0e4..fb7b03ec2071 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt +++ b/Documentation/devicetree/bindings/board/fsl-board.txt @@ -21,11 +21,14 @@ Example: This is the memory-mapped registers for on board FPGA. -Required properities: +Required properties: - compatible: should be a board-specific string followed by a string indicating the type of FPGA. Example: - "fsl,<board>-fpga", "fsl,fpga-pixis" + "fsl,<board>-fpga", "fsl,fpga-pixis", or + "fsl,<board>-fpga", "fsl,fpga-qixis" - reg: should contain the address and the length of the FPGA register set. + +Optional properties: - interrupt-parent: should specify phandle for the interrupt controller. - interrupts: should specify event (wakeup) IRQ. @@ -38,6 +41,13 @@ Example (P1022DS): interrupts = <8 8 0 0>; }; +Example (LS2080A-RDB): + + cpld@3,0 { + compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis"; + reg = <0x3 0 0x10000>; + }; + * Freescale BCSR GPIO banks Some BCSR registers act as simple GPIO controllers, each such |