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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-01-13 16:48:53 +0200 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@microchip.com> | 2022-02-25 12:36:25 +0100 |
| commit | 9a0775c9cd3d89d1fe957a137131681a33f5736b (patch) | |
| tree | 562eec472c45cf21354d65e07e41fcfeaf9088bd | |
| parent | 55614e682a2c9fac12a0f121b43b93ff4915d0e6 (diff) | |
| download | linux-9a0775c9cd3d89d1fe957a137131681a33f5736b.tar.bz2 | |
ARM: at91: ddr: fix typo to align with datasheet naming
Fix typo on UDDRC_PWRCTL.SELFREF_SW bitmask to align with datasheet
naming.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220113144900.906370-4-claudiu.beznea@microchip.com
| -rw-r--r-- | arch/arm/mach-at91/pm_suspend.S | 4 | ||||
| -rw-r--r-- | include/soc/at91/sama7-ddr.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index fdb4f63ecde4..abe4ced33eda 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -159,7 +159,7 @@ sr_ena_1: /* Switch to self-refresh. */ ldr tmp1, [r2, #UDDRC_PWRCTL] - orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW + orr tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW str tmp1, [r2, #UDDRC_PWRCTL] sr_ena_2: @@ -276,7 +276,7 @@ sr_dis_5: /* Trigger self-refresh exit. */ ldr tmp1, [r2, #UDDRC_PWRCTL] - bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW + bic tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW str tmp1, [r2, #UDDRC_PWRCTL] sr_dis_6: diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index 817b360efbb8..fee1b11bddca 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -53,7 +53,7 @@ #define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ -#define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */ +#define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */ #define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ #define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */ |