diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-12-12 23:17:38 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-10-29 17:32:20 +0200 |
| commit | 96eaeb3dfa40576a7aa195303c538202311cffbc (patch) | |
| tree | 726d74d01730d614f64014fd1e49a9531036a118 | |
| parent | bd0cef2a797ac59a103c887b7864b6cf7bd5b512 (diff) | |
| download | linux-96eaeb3dfa40576a7aa195303c538202311cffbc.tar.bz2 | |
drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers
Remove the hand rolled array of WM0_PIPE register offsets
and use the standard _MMIO_PIPE3() instead.
v2: Take care of gvt too
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212211738.27770-1-ville.syrjala@linux.intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 13 |
3 files changed, 12 insertions, 16 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index e0edc9d1f357..c7cf15fe9ef6 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2209,9 +2209,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_D(PF_VSCALE(PIPE_C), D_ALL); MMIO_D(PF_HSCALE(PIPE_C), D_ALL); - MMIO_D(WM0_PIPEA_ILK, D_ALL); - MMIO_D(WM0_PIPEB_ILK, D_ALL); - MMIO_D(WM0_PIPEC_IVB, D_ALL); + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL); + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL); + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL); MMIO_D(WM1_LP_ILK, D_ALL); MMIO_D(WM2_LP_ILK, D_ALL); MMIO_D(WM3_LP_ILK, D_ALL); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8b021f77cb1f..993d0b4c6cf3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6434,15 +6434,16 @@ enum { _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) /* define the Watermark register on Ironlake */ -#define WM0_PIPEA_ILK _MMIO(0x45100) +#define _WM0_PIPEA_ILK 0x45100 +#define _WM0_PIPEB_ILK 0x45104 +#define _WM0_PIPEC_IVB 0x45200 +#define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ + _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) #define WM0_PIPE_PLANE_MASK (0xffff << 16) #define WM0_PIPE_PLANE_SHIFT 16 #define WM0_PIPE_SPRITE_MASK (0xff << 8) #define WM0_PIPE_SPRITE_SHIFT 8 #define WM0_PIPE_CURSOR_MASK (0xff) - -#define WM0_PIPEB_ILK _MMIO(0x45104) -#define WM0_PIPEC_IVB _MMIO(0x45200) #define WM1_LP_ILK _MMIO(0x45108) #define WM1_LP_SR_EN (1 << 31) #define WM1_LP_LATENCY_SHIFT 24 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0ef01a01ef8d..f54375b11964 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3573,11 +3573,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, _ilk_disable_lp_wm(dev_priv, dirty); if (dirty & WM_DIRTY_PIPE(PIPE_A)) - I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); + I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]); if (dirty & WM_DIRTY_PIPE(PIPE_B)) - I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); + I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]); if (dirty & WM_DIRTY_PIPE(PIPE_C)) - I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); + I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]); if (dirty & WM_DIRTY_DDB) { if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@ -6287,13 +6287,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal; enum pipe pipe = crtc->pipe; - static const i915_reg_t wm0_pipe_reg[] = { - [PIPE_A] = WM0_PIPEA_ILK, - [PIPE_B] = WM0_PIPEB_ILK, - [PIPE_C] = WM0_PIPEC_IVB, - }; - hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); + hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe)); memset(active, 0, sizeof(*active)); |