diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-12-12 10:17:08 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-12-12 10:17:08 -0800 |
| commit | 8e17b16a2c13406c56a4d292df3ca083f8729666 (patch) | |
| tree | 30bb0fe90b00e857bb708aaa3605f671a66e8101 | |
| parent | 69700db4212ac784130f63a350b1ede3b7184494 (diff) | |
| parent | 9379885d07c466a9207e88c0fd0c8b3541536fe3 (diff) | |
| download | linux-8e17b16a2c13406c56a4d292df3ca083f8729666.tar.bz2 | |
Merge tag 'soc-drivers-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"There are few major updates in the SoC specific drivers, mainly the
usual reworks and support for variants of the existing SoC. While this
remains Arm centric for the most part, the branch now also contains
updates to risc-v and loongarch specific code in drivers/soc/.
Notable changes include:
- Support for the newly added Qualcomm Snapdragon variants (MSM8956,
MSM8976, SM6115, SM4250, SM8150, SA8155 and SM8550) in the soc ID,
rpmh, rpm, spm and powerdomain drivers.
- Documentation for the somewhat controversial qcom,board-id
properties that are required for booting a number of machines
- A new SoC identification driver for the loongson-2 (loongarch)
platform
- memory controller updates for stm32, tegra, and renesas.
- a new DT binding to better describe LPDDR2/3/4/5 chips in the
memory controller subsystem
- Updates for Tegra specific drivers across multiple subsystems,
improving support for newer SoCs and better identification
- Minor fixes for Broadcom, Freescale, Apple, Renesas, Sifive, TI,
Mediatek and Marvell SoC drivers"
* tag 'soc-drivers-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (137 commits)
soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id table
dt-bindings: arm: qcom,ids: Add SoC IDs for SM6115 / SM4250 and variants
soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id table
dt-bindings: arm: qcom,ids: Add SoC IDs for SM8150 and SA8155
dt-bindings: soc: qcom: apr: document generic qcom,apr compatible
soc: qcom: Select REMAP_MMIO for ICC_BWMON driver
soc: qcom: Select REMAP_MMIO for LLCC driver
soc: qcom: rpmpd: Add SM4250 support
dt-bindings: power: rpmpd: Add SM4250 support
dt-bindings: soc: qcom: aoss: Add compatible for SM8550
soc: qcom: llcc: Add configuration data for SM8550
dt-bindings: arm: msm: Add LLCC compatible for SM8550
soc: qcom: llcc: Add v4.1 HW version support
soc: qcom: socinfo: Add SM8550 ID
soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done response
soc: qcom: rpmh-rsc: Add support for RSC v3 register offsets
soc: qcom: rpmhpd: Add SM8550 power domains
dt-bindings: power: rpmpd: Add SM8550 to rpmpd binding
soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id table
dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976
...
118 files changed, 6540 insertions, 1876 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index eb451bec23d3..0711f1834fbd 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -32,14 +32,26 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8192-mmsys - - mediatek,mt8195-mmsys - mediatek,mt8365-mmsys - const: syscon + + - description: vdosys0 and vdosys1 are 2 display HW pipelines, + so mt8195 binding should be deprecated. + deprecated: true + items: + - const: mediatek,mt8195-mmsys + - const: syscon + - items: - const: mediatek,mt7623-mmsys - const: mediatek,mt2701-mmsys - const: syscon + - items: + - const: mediatek,mt8195-vdosys0 + - const: mediatek,mt8195-mmsys + - const: syscon + reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 5ea506412b4e..38efcad56dbd 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -31,6 +31,7 @@ properties: - qcom,sm8250-llcc - qcom,sm8350-llcc - qcom,sm8450-llcc + - qcom,sm8550-llcc reg: items: diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1b5ac6b02bc5..b8341967240b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -739,6 +739,126 @@ properties: - sony,pdx223 - const: qcom,sm8450 + # Board compatibles go above + + qcom,msm-id: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 8 + items: + items: + - description: | + MSM chipset ID - an exact match value consisting of two bitfields:: + - bits 0-15 - The unique MSM chipset ID + - bits 16-31 - Reserved; should be 0 + - description: | + Hardware revision ID - a chipset specific 32-bit ID representing + the version of the chipset. It is best a match value - the + bootloader will look for the closest possible match. + deprecated: true + description: + The MSM chipset and hardware revision used Qualcomm bootloaders. It + can optionally be an array of these to indicate multiple hardware that + use the same device tree. It is expected that the bootloader will use + this information at boot-up to decide which device tree to use when given + multiple device trees, some of which may not be compatible with the + actual hardware. It is the bootloader's responsibility to pass the + correct device tree to the kernel. + The property is deprecated. + + qcom,board-id: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 8 + oneOf: + - items: + - items: + - description: | + Board ID consisting of three bitfields:: + - bits 31-24 - Unused + - bits 23-16 - Platform Version Major + - bits 15-8 - Platform Version Minor + - bits 7-0 - Platform Type + Platform Type field is an exact match value. The + Platform Major/Minor field is a best match. The bootloader will + look for the closest possible match. + - description: | + Subtype ID unique to a Platform Type/Chipset ID. For a given + Platform Type, there will typically only be a single board and the + subtype_id will be 0. However in some cases board variants may + need to be distinguished by different subtype_id values. + - items: + # OnePlus uses a variant of board-id with four elements: + - items: + - const: 8 + - const: 0 + - description: OnePlus board ID + - description: OnePlus subtype ID + deprecated: true + description: + The board type and revision information. It can optionally be an array + of these to indicate multiple boards that use the same device tree. It + is expected that the bootloader will use this information at boot-up to + decide which device tree to use when given multiple device trees, some of + which may not be compatible with the actual hardware. It is the + bootloader's responsibility to pass the correct device tree to the + kernel + The property is deprecated. + +allOf: + # Explicit allow-list for older SoCs. The legacy properties are not allowed + # on newer SoCs. + - if: + properties: + compatible: + contains: + enum: + - qcom,apq8026 + - qcom,apq8094 + - qcom,apq8096 + - qcom,msm8992 + - qcom,msm8994 + - qcom,msm8996 + - qcom,msm8998 + - qcom,sdm630 + - qcom,sdm632 + - qcom,sdm845 + - qcom,sdx55 + - qcom,sdx65 + - qcom,sm6125 + - qcom,sm6350 + - qcom,sm7225 + - qcom,sm8150 + - qcom,sm8250 + then: + properties: + qcom,board-id: true + qcom,msm-id: true + else: + properties: + qcom,board-id: false + qcom,msm-id: false + + - if: + properties: + compatible: + contains: + enum: + - oneplus,cheeseburger + - oneplus,dumpling + - oneplus,enchilada + - oneplus,fajita + then: + properties: + qcom,board-id: + items: + minItems: 4 + else: + properties: + qcom,board-id: + items: + maxItems: 2 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index c5b76c9f7ad0..25688571ee7c 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -41,12 +41,14 @@ properties: - qcom,scm-sc7180 - qcom,scm-sc7280 - qcom,scm-sc8280xp + - qcom,scm-sdm670 - qcom,scm-sdm845 - qcom,scm-sdx55 - qcom,scm-sdx65 - qcom,scm-sm6115 - qcom,scm-sm6125 - qcom,scm-sm6350 + - qcom,scm-sm6375 - qcom,scm-sm8150 - qcom,scm-sm8250 - qcom,scm-sm8350 @@ -88,6 +90,7 @@ allOf: - qcom,scm-apq8064 - qcom,scm-msm8660 - qcom,scm-msm8960 + - qcom,scm-sm6375 then: properties: clock-names: diff --git a/Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml b/Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml new file mode 100644 index 000000000000..9d0c36ec1982 --- /dev/null +++ b/Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwinfo/loongson,ls2k-chipid.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-2 SoC ChipID + +maintainers: + - Yinbo Zhu <zhuyinbo@loongson.cn> + +description: | + Loongson-2 SoC contains many groups of global utilities register + blocks, of which the ChipID group registers record SoC version, + feature, vendor and id information. + +properties: + compatible: + const: loongson,ls2k-chipid + + reg: + maxItems: 1 + + little-endian: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + chipid: chipid@1fe00000 { + compatible = "loongson,ls2k-chipid"; + reg = <0x1fe00000 0x3ffc>; + little-endian; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml b/Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml index 01c9acf9275d..bd23257fe021 100644 --- a/Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml @@ -1,26 +1,31 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml# +$id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM PL353 Static Memory Controller (SMC) device-tree bindings +title: Arm PL35x Series Static Memory Controller (SMC) maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> -description: - The PL353 Static Memory Controller is a bus where you can connect two kinds +description: | + The PL35x Static Memory Controller is a bus where you can connect two kinds of memory interfaces, which are NAND and memory mapped interfaces (such as - SRAM or NOR). + SRAM or NOR) depending on the specific configuration. + + The TRM is available here: + https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa # We need a select here so we don't match all nodes with 'arm,primecell' select: properties: compatible: contains: - const: arm,pl353-smc-r2p1 + enum: + - arm,pl353-smc-r2p1 + - arm,pl354 required: - compatible @@ -30,7 +35,9 @@ properties: compatible: items: - - const: arm,pl353-smc-r2p1 + - enum: + - arm,pl353-smc-r2p1 + - arm,pl354 - const: arm,primecell "#address-cells": @@ -46,30 +53,25 @@ properties: The three chip select regions are defined in 'ranges'. clocks: - items: - - description: clock for the memory device bus - - description: main clock of the SMC + minItems: 1 + maxItems: 2 clock-names: - items: - - const: memclk - - const: apb_pclk + minItems: 1 + maxItems: 2 ranges: minItems: 1 - description: | - Memory bus areas for interacting with the devices. Reflects - the memory layout with four integer values following: - <cs-number> 0 <offset> <size> - items: - - description: NAND bank 0 - - description: NOR/SRAM bank 0 - - description: NOR/SRAM bank 1 + maxItems: 8 - interrupts: true + interrupts: + minItems: 1 + items: + - description: Combined or Memory interface 0 IRQ + - description: Memory interface 1 IRQ patternProperties: - "@[0-3],[a-f0-9]+$": + "@[0-7],[a-f0-9]+$": type: object description: | The child device node represents the controller connected to the SMC @@ -87,7 +89,7 @@ patternProperties: - description: | Chip-select ID, as in the parent range property. minimum: 0 - maximum: 2 + maximum: 7 - description: | Offset of the memory region requested by the device. - description: | @@ -102,12 +104,36 @@ required: - reg - clock-names - clocks - - "#address-cells" - - "#size-cells" - - ranges additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: arm,pl354 + then: + properties: + clocks: + # According to TRM, really should be 3 clocks + maxItems: 1 + + clock-names: + const: apb_pclk + + else: + properties: + clocks: + items: + - description: clock for the memory device bus + - description: main clock of the SMC + + clock-names: + items: + - const: memclk + - const: apb_pclk + examples: - | smcc: memory-controller@e000e000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml new file mode 100644 index 000000000000..34b5bd153f63 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-channel.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR channel with chip/rank topology description + +description: + An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS, + CK, etc.) that connect one or more LPDDR chips to a host system. The main + purpose of this node is to overall LPDDR topology of the system, including the + amount of individual LPDDR chips and the ranks per chip. + +maintainers: + - Julius Werner <jwerner@chromium.org> + +properties: + compatible: + enum: + - jedec,lpddr2-channel + - jedec,lpddr3-channel + - jedec,lpddr4-channel + - jedec,lpddr5-channel + + io-width: + description: + The number of DQ pins in the channel. If this number is different + from (a multiple of) the io-width of the LPDDR chip, that means that + multiple instances of that type of chip are wired in parallel on this + channel (with the channel's DQ pins split up between the different + chips, and the CA, CS, etc. pins of the different chips all shorted + together). This means that the total physical memory controlled by a + channel is equal to the sum of the densities of each rank on the + connected LPDDR chip, times the io-width of the channel divided by + the io-width of the LPDDR chip. + enum: + - 8 + - 16 + - 32 + - 64 + - 128 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^rank@[0-9]+$": + type: object + description: + Each physical LPDDR chip may have one or more ranks. Ranks are + internal but fully independent sub-units of the chip. Each LPDDR bus + transaction on the channel targets exactly one rank, based on the + state of the CS pins. Different ranks may have different densities and + timing requirements. + required: + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: jedec,lpddr2-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml# + - if: + properties: + compatible: + contains: + const: jedec,lpddr3-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml# + - if: + properties: + compatible: + contains: + const: jedec,lpddr4-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml# + - if: + properties: + compatible: + contains: + const: jedec,lpddr5-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml# + +required: + - compatible + - io-width + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + lpddr-channel0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,lpddr3-channel"; + io-width = <32>; + + rank@0 { + compatible = "lpddr3-ff,0100", "jedec,lpddr3"; + reg = <0>; + density = <8192>; + io-width = <16>; + revision-id = <1 0>; + }; + }; + + lpddr-channel1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,lpddr4-channel"; + io-width = <32>; + + rank@0 { + compatible = "lpddr4-05,0301", "jedec,lpddr4"; + reg = <0>; + density = <4096>; + io-width = <32>; + revision-id = <3 1>; + }; + + rank@1 { + compatible = "lpddr4-05,0301", "jedec,lpddr4"; + reg = <1>; + density = <2048>; + io-width = <32>; + revision-id = <3 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml new file mode 100644 index 000000000000..30267ce70124 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-props.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for LPDDR types + +description: + Different LPDDR types generally use the same properties and only differ in the + range of legal values for each. This file defines the common parts that can be + reused for each type. Nodes using this schema should generally be nested under + an LPDDR channel node. + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + compatible: + description: + Compatible strings can be either explicit vendor names and part numbers + (e.g. elpida,ECB240ABACN), or generated strings of the form + lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID + (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are + formatted in lower case hexadecimal representation with leading zeroes. + The latter form can be useful when LPDDR nodes are created at runtime by + boot firmware that doesn't have access to static part number information. + + reg: + description: + The rank number of this LPDDR rank when used as a subnode to an LPDDR + channel. + minimum: 0 + maximum: 3 + + revision-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>). + maxItems: 2 + items: + minimum: 0 + maximum: 255 + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Density in megabits of SDRAM chip. Decoded from Mode Register 8. + enum: + - 64 + - 128 + - 256 + - 512 + - 1024 + - 2048 + - 3072 + - 4096 + - 6144 + - 8192 + - 12288 + - 16384 + - 24576 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + IO bus width in bits of SDRAM chip. Decoded from Mode Register 8. + enum: + - 8 + - 16 + - 32 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml index 9d78f140609b..a237bc259273 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml @@ -9,6 +9,9 @@ title: LPDDR2 SDRAM compliant to JEDEC JESD209-2 maintainers: - Krzysztof Kozlowski <krzk@kernel.org> +allOf: + - $ref: jedec,lpddr-props.yaml# + properties: compatible: oneOf: @@ -17,13 +20,15 @@ properties: - elpida,ECB240ABACN - elpida,B8132B2PB-6D-F - enum: - - jedec,lpddr2-s4 - - items: - - enum: + - jedec,lpddr2-nvm - jedec,lpddr2-s2 + - jedec,lpddr2-s4 - items: + - pattern: "^lpddr2-[0-9a-f]{2},[0-9a-f]{4}$" - enum: - jedec,lpddr2-nvm + - jedec,lpddr2-s2 + - jedec,lpddr2-s4 revision-id1: $ref: /schemas/types.yaml#/definitions/uint32 @@ -41,41 +46,6 @@ properties: Property is deprecated, use revision-id instead. deprecated: true - revision-id: - $ref: /schemas/types.yaml#/definitions/uint32-array - description: | - Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>). - minItems: 2 - maxItems: 2 - items: - minimum: 0 - maximum: 255 - - density: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Density in megabits of SDRAM chip. Obtained from device datasheet. - enum: - - 64 - - 128 - - 256 - - 512 - - 1024 - - 2048 - - 4096 - - 8192 - - 16384 - - 32768 - - io-width: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - IO bus width in bits of SDRAM chip. Obtained from device datasheet. - enum: - - 32 - - 16 - - 8 - tRRD-min-tck: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 16 @@ -168,7 +138,7 @@ required: - density - io-width -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index 48908a19473c..e328a1195ba6 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -9,35 +9,24 @@ title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 maintainers: - Krzysztof Kozlowski <krzk@kernel.org> +allOf: + - $ref: jedec,lpddr-props.yaml# + properties: compatible: - items: - - enum: - - samsung,K3QF2F20DB - - const: jedec,lpddr3 + oneOf: + - items: + - enum: + - samsung,K3QF2F20DB + - const: jedec,lpddr3 + - items: + - pattern: "^lpddr3-[0-9a-f]{2},[0-9a-f]{4}$" + - const: jedec,lpddr3 '#address-cells': const: 1 deprecated: true - density: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Density in megabits of SDRAM chip. - enum: - - 4096 - - 8192 - - 16384 - - 32768 - - io-width: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - IO bus width in bits of SDRAM chip. - enum: - - 32 - - 16 - manufacturer-id: $ref: /schemas/types.yaml#/definitions/uint32 description: | @@ -45,15 +34,6 @@ properties: deprecated, manufacturer should be derived from the compatible. deprecated: true - revision-id: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 2 - maxItems: 2 - items: - maximum: 255 - description: | - Revision value of SDRAM chip read from Mode Registers 6 and 7. - '#size-cells': const: 0 deprecated: true @@ -206,7 +186,7 @@ required: - density - io-width -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml new file mode 100644 index 000000000000..a078892fecee --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR4 SDRAM compliant to JEDEC JESD209-4 + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +allOf: + - $ref: jedec,lpddr-props.yaml# + +properties: + compatible: + items: + - pattern: "^lpddr4-[0-9a-f]{2},[0-9a-f]{4}$" + - const: jedec,lpddr4 + +required: + - compatible + - density + - io-width + +unevaluatedProperties: false + +examples: + - | + lpddr { + compatible = "lpddr4-ff,0100", "jedec,lpddr4"; + density = <8192>; + io-width = <16>; + revision-id = <1 0>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml new file mode 100644 index 000000000000..e441dac5f154 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR5 SDRAM compliant to JEDEC JESD209-5 + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +allOf: + - $ref: jedec,lpddr-props.yaml# + +properties: + compatible: + items: + - pattern: "^lpddr5-[0-9a-f]{2},[0-9a-f]{4}$" + - const: jedec,lpddr5 + + serial-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Serial IDs read from Mode Registers 47 through 54. One byte per uint32 + cell (i.e. <MR47 MR48 MR49 MR50 MR51 MR52 MR53 MR54>). + maxItems: 8 + items: + minimum: 0 + maximum: 255 + +required: + - compatible + - density + - io-width + +unevaluatedProperties: false + +examples: + - | + lpddr { + compatible = "lpddr5-01,0200", "jedec,lpddr5"; + density = <8192>; + io-width = <8>; + revision-id = <2 0>; + serial-id = <3 1 0 0 0 0 0 0>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml new file mode 100644 index 000000000000..53ae995462db --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral-specific properties for a Memory Controller bus. + +description: + Many Memory Controllers need to add properties to peripheral devices. + They could be common properties like reg or they could be controller + specific like delay in clock or data lines, etc. These properties need + to be defined in the peripheral node because they are per-peripheral + and there can be multiple peripherals attached to a controller. All + those properties are listed here. The controller specific properties + should go in their own separate schema that should be referenced + from here. + +maintainers: + - Marek Vasut <marex@denx.de> + +properties: + reg: + description: Bank number, base address and size of the device. + + bank-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bank width of the device, in bytes. + enum: [1, 2, 4] + +required: + - reg + +# The controller specific properties go here. +allOf: + - $ref: st,stm32-fmc2-ebi-props.yaml# + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index 645249ea21d1..30a403b1b79a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -44,6 +44,11 @@ properties: - items: - enum: + - renesas,r8a779g0-rpc-if # R-Car V4H + - const: renesas,rcar-gen4-rpc-if # a generic R-Car gen4 device + + - items: + - enum: - renesas,r9a07g043-rpc-if # RZ/G2UL - renesas,r9a07g044-rpc-if # RZ/G2{L,LC} - renesas,r9a07g054-rpc-if # RZ/V2L diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi-props.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi-props.yaml new file mode 100644 index 000000000000..475e4095068c --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi-props.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral properties for ST FMC2 Controller + +maintainers: + - Christophe Kerello <christophe.kerello@foss.st.com> + - Marek Vasut <marex@denx.de> + +properties: + st,fmc2-ebi-cs-transaction-type: + description: | + Select one of the transactions type supported + 0: Asynchronous mode 1 SRAM/FRAM. + 1: Asynchronous mode 1 PSRAM. + 2: Asynchronous mode A SRAM/FRAM. + 3: Asynchronous mode A PSRAM. + 4: Asynchronous mode 2 NOR. + 5: Asynchronous mode B NOR. + 6: Asynchronous mode C NOR. + 7: Asynchronous mode D NOR. + 8: Synchronous read synchronous write PSRAM. + 9: Synchronous read asynchronous write PSRAM. + 10: Synchronous read synchronous write NOR. + 11: Synchronous read asynchronous write NOR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 11 + + st,fmc2-ebi-cs-cclk-enable: + description: Continuous clock enable (first bank must be configured + in synchronous mode). The FMC_CLK is generated continuously + during asynchronous and synchronous access. By default, the + FMC_CLK is only generated during synchronous access. + $ref: /schemas/types.yaml#/definitions/flag + + st,fmc2-ebi-cs-mux-enable: + description: Address/Data multiplexed on databus (valid only with + NOR and PSRAM transactions type). By default, Address/Data + are not multiplexed. + $ref: /schemas/types.yaml#/definitions/flag + + st,fmc2-ebi-cs-buswidth: + description: Data bus width + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 8, 16 ] + default: 16 + + st,fmc2-ebi-cs-waitpol-high: + description: Wait signal polarity (NWAIT signal active high). + By default, NWAIT is active low. + $ref: /schemas/types.yaml#/definitions/flag + + st,fmc2-ebi-cs-waitcfg-enable: + description: The NWAIT signal indicates wheither the data from the + device are valid or if a wait state must be inserted when accessing + the device in synchronous mode. By default, the NWAIT signal is + active one data cycle before wait state. + $ref: /schemas/types.yaml#/definitions/flag + + st,fmc2-ebi-cs-wait-enable: + description: The NWAIT signal is enabled (its level is taken into + account after the programmed latency period to insert wait states + if asserted). By default, the NWAIT signal is disabled. + $ref: /schemas/types.yaml#/definitions/flag + + st,fmc2-ebi-cs-asyncwait-enable: + description: The NWAIT signal is taken into account during asynchronous + transactions. By default, the NWAIT signal is not taken into account + during asynchronous transactions. + $ref: /schemas/types.yaml#/definitions/flag + + st,fmc2-ebi-cs-cpsize: + description: CRAM page size. The controller splits the burst access + when the memory page is reached. By default, no burst split when + crossing page boundary. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 128, 256, 512, 1024 ] + default: 0 + + st,fmc2-ebi-cs-byte-lane-setup-ns: + description: This property configures the byte lane setup timing + defined in nanoseconds from NBLx low to Chip Select NEx low. + + st,fmc2-ebi-cs-address-setup-ns: + description: This property defines the duration of the address setup + phase in nanoseconds used for asynchronous read/write transactions. + + st,fmc2-ebi-cs-address-hold-ns: + description: This property defines the duration of the address hold + phase in nanoseconds used for asynchronous multiplexed read/write + transactions. + + st,fmc2-ebi-cs-data-setup-ns: + description: This property defines the duration of the data setup phase + in nanoseconds used for asynchronous read/write transactions. + + st,fmc2-ebi-cs-bus-turnaround-ns: + description: This property defines the delay in nanoseconds between the + end of current read/write transaction and the next transaction. + + st,fmc2-ebi-cs-data-hold-ns: + description: This property defines the duration of the data hold phase + in nanoseconds used for asynchronous read/write transactions. + + st,fmc2-ebi-cs-clk-period-ns: + description: This property defines the FMC_CLK output signal period in + nanoseconds. + + st,fmc2-ebi-cs-data-latency-ns: + description: This property defines the data latency before reading or + writing the first data in nanoseconds. + + st,fmc2-ebi-cs-write-address-setup-ns: + description: This property defines the duration of the address setup + phase in nanoseconds used for asynchronous write transactions. + + st,fmc2-ebi-cs-write-address-hold-ns: + description: This property defines the duration of the address hold + phase in nanoseconds used for asynchronous multiplexed write + transactions. + + st,fmc2-ebi-cs-write-data-setup-ns: + description: This property defines the duration of the data setup + phase in nanoseconds used for asynchronous write transactions. + + st,fmc2-ebi-cs-write-bus-turnaround-ns: + description: This property defines the delay between the end of current + write transaction and the next transaction in nanoseconds. + + st,fmc2-ebi-cs-write-data-hold-ns: + description: This property defines the duration of the data hold phase + in nanoseconds used for asynchronous write transactions. + + st,fmc2-ebi-cs-max-low-pulse-ns: + description: This property defines the maximum chip select low pulse + duration in nanoseconds for synchronous transactions. When this timing + reaches 0, the controller splits the current access, toggles NE to + allow device refresh and restarts a new access. + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 6b516d3895af..d71af02b7f16 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -48,143 +48,7 @@ properties: patternProperties: "^.*@[0-4],[a-f0-9]+$": type: object - - properties: - reg: - description: Bank number, base address and size of the device. - - st,fmc2-ebi-cs-transaction-type: - description: | - Select one of the transactions type supported - 0: Asynchronous mode 1 SRAM/FRAM. - 1: Asynchronous mode 1 PSRAM. - 2: Asynchronous mode A SRAM/FRAM. - 3: Asynchronous mode A PSRAM. - 4: Asynchronous mode 2 NOR. - 5: Asynchronous mode B NOR. - 6: Asynchronous mode C NOR. - 7: Asynchronous mode D NOR. - 8: Synchronous read synchronous write PSRAM. - 9: Synchronous read asynchronous write PSRAM. - 10: Synchronous read synchronous write NOR. - 11: Synchronous read asynchronous write NOR. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 11 - - st,fmc2-ebi-cs-cclk-enable: - description: Continuous clock enable (first bank must be configured - in synchronous mode). The FMC_CLK is generated continuously - during asynchronous and synchronous access. By default, the - FMC_CLK is only generated during synchronous access. - $ref: /schemas/types.yaml#/definitions/flag - - st,fmc2-ebi-cs-mux-enable: - description: Address/Data multiplexed on databus (valid only with - NOR and PSRAM transactions type). By default, Address/Data - are not multiplexed. - $ref: /schemas/types.yaml#/definitions/flag - - st,fmc2-ebi-cs-buswidth: - description: Data bus width - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [ 8, 16 ] - default: 16 - - st,fmc2-ebi-cs-waitpol-high: - description: Wait signal polarity (NWAIT signal active high). - By default, NWAIT is active low. - $ref: /schemas/types.yaml#/definitions/flag - - st,fmc2-ebi-cs-waitcfg-enable: - description: The NWAIT signal indicates wheither the data from the - device are valid or if a wait state must be inserted when accessing - the device in synchronous mode. By default, the NWAIT signal is - active one data cycle before wait state. - $ref: /schemas/types.yaml#/definitions/flag - - st,fmc2-ebi-cs-wait-enable: - description: The NWAIT signal is enabled (its level is taken into - account after the programmed latency period to insert wait states - if asserted). By default, the NWAIT signal is disabled. - $ref: /schemas/types.yaml#/definitions/flag - - st,fmc2-ebi-cs-asyncwait-enable: - description: The NWAIT signal is taken into account during asynchronous - transactions. By default, the NWAIT signal is not taken into account - during asynchronous transactions. - $ref: /schemas/types.yaml#/definitions/flag - - st,fmc2-ebi-cs-cpsize: - description: CRAM page size. The controller splits the burst access - when the memory page is reached. By default, no burst split when - crossing page boundary. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [ 0, 128, 256, 512, 1024 ] - default: 0 - - st,fmc2-ebi-cs-byte-lane-setup-ns: - description: This property configures the byte lane setup timing - defined in nanoseconds from NBLx low to Chip Select NEx low. - - st,fmc2-ebi-cs-address-setup-ns: - description: This property defines the duration of the address setup - phase in nanoseconds used for asynchronous read/write transactions. - - st,fmc2-ebi-cs-address-hold-ns: - description: This property defines the duration of the address hold - phase in nanoseconds used for asynchronous multiplexed read/write - transactions. - - st,fmc2-ebi-cs-data-setup-ns: - description: This property defines the duration of the data setup phase - in nanoseconds used for asynchronous read/write transactions. - - st,fmc2-ebi-cs-bus-turnaround-ns: - description: This property defines the delay in nanoseconds between the - end of current read/write transaction and the next transaction. - - st,fmc2-ebi-cs-data-hold-ns: - description: This property defines the duration of the data hold phase - in nanoseconds used for asynchronous read/write transactions. - - st,fmc2-ebi-cs-clk-period-ns: - description: This property defines the FMC_CLK output signal period in - nanoseconds. - - st,fmc2-ebi-cs-data-latency-ns: - description: This property defines the data latency before reading or - writing the first data in nanoseconds. - - st,fmc2_ebi-cs-write-address-setup-ns: - description: This property defines the duration of the address setup - phase in nanoseconds used for asynchronous write transactions. - - st,fmc2-ebi-cs-write-address-hold-ns: - description: This property defines the duration of the address hold - phase in nanoseconds used for asynchronous multiplexed write - transactions. - - st,fmc2-ebi-cs-write-data-setup-ns: - description: This property defines the duration of the data setup - phase in nanoseconds used for asynchronous write transactions. - - st,fmc2-ebi-cs-write-bus-turnaround-ns: - description: This property defines the delay between the end of current - write transaction and the next transaction in nanoseconds. - - st,fmc2-ebi-cs-write-data-hold-ns: - description: This property defines the duration of the data hold phase - in nanoseconds used for asynchronous write transactions. - - st,fmc2-ebi-cs-max-low-pulse-ns: - description: This property defines the maximum chip select low pulse - duration in nanoseconds for synchronous transactions. When this timing - reaches 0, the controller splits the current access, toggles NE to - allow device refresh and restarts a new access. - - required: - - reg + $ref: mc-peripheral-props.yaml# required: - "#address-cells" diff --git a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc-child.yaml b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc-child.yaml index 6e3995bb1630..4a257fac577e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc-child.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc-child.yaml @@ -230,6 +230,13 @@ properties: Wait-pin used by client. Must be less than "gpmc,num-waitpins". $ref: /schemas/types.yaml#/definitions/uint32 + ti,wait-pin-polarity: + description: | + Set the desired polarity for the selected wait pin. + 0 for active low, 1 for active high. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + gpmc,wait-on-read: description: Enables wait monitoring on reads. type: boolean diff --git a/Documentation/devicetree/bindings/net/micrel,ks8851.yaml b/Documentation/devicetree/bindings/net/micrel,ks8851.yaml index 5aa7cf2eacb1..b44d83554ef5 100644 --- a/Documentation/devicetree/bindings/net/micrel,ks8851.yaml +++ b/Documentation/devicetree/bindings/net/micrel,ks8851.yaml @@ -44,6 +44,7 @@ required: allOf: - $ref: ethernet-controller.yaml# + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 5b4eda919911..633d49884019 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -28,15 +28,18 @@ properties: - qcom,msm8998-rpmpd - qcom,qcm2290-rpmpd - qcom,qcs404-rpmpd + - qcom,qdu1000-rpmhpd - qcom,sa8540p-rpmhpd - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd - qcom,sc7280-rpmhpd - qcom,sc8180x-rpmhpd - qcom,sc8280xp-rpmhpd + - qcom,sdm670-rpmhpd - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd + - qcom,sm4250-rpmpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd @@ -45,6 +48,7 @@ properties: - qcom,sm8250-rpmhpd - qcom,sm8350-rpmhpd - qcom,sm8450-rpmhpd + - qcom,sm8550-rpmhpd '#power-domain-cells': const: 1 diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt index d24e2bc444be..12e4b4260b40 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -30,6 +30,7 @@ Required properties in pwrap device node. "mediatek,mt8186-pwrap" for MT8186 SoCs "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs "mediatek,mt8195-pwrap" for MT8195 SoCs + "mediatek,mt8365-pwrap" for MT8365 SoCs "mediatek,mt8516-pwrap" for MT8516 SoCs - interrupts: IRQ for pwrap in SOC - reg-names: "pwrap" is required; "pwrap-bridge" is optional. @@ -39,6 +40,8 @@ Required properties in pwrap device node. - clock-names: Must include the following entries: "spi": SPI bus clock "wrap": Main module clock + "sys": Optional system module clock + "tmr": Optional timer module clock - clocks: Must contain an entry for each entry in clock-names. Optional properities: diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index a4eeb7e158e5..98d087cf4fc0 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -28,12 +28,14 @@ properties: - qcom,sc7180-aoss-qmp - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp + - qcom,sc8280xp-aoss-qmp - qcom,sdm845-aoss-qmp - qcom,sm6350-aoss-qmp - qcom,sm8150-aoss-qmp - qcom,sm8250-aoss-qmp - qcom,sm8350-aoss-qmp - qcom,sm8450-aoss-qmp + - qcom,sm8550-aoss-qmp - const: qcom,aoss-qmp reg: diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml index f47491aab3b1..857f8b886c10 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - qcom,apr - qcom,apr-v2 - qcom,gpr diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index 4a50f1d27724..b246500d3d5d 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -99,6 +99,9 @@ properties: - const: drv-2 - const: drv-3 + power-domains: + maxItems: 1 + bcm-voter: $ref: /schemas/interconnect/qcom,bcm-voter.yaml# @@ -151,6 +154,7 @@ examples: <SLEEP_TCS 3>, <WAKE_TCS 3>, <CONTROL_TCS 1>; + power-domains = <&CLUSTER_PD>; }; - | @@ -197,6 +201,7 @@ examples: <SLEEP_TCS 3>, <WAKE_TCS 3>, <CONTROL_TCS 0>; + power-domains = <&CLUSTER_PD>; clock-controller { compatible = "qcom,sm8350-rpmh-clk"; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 09d5bfa920f2..11c0f4dd797c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/soc/qcom/qcom,smd-rpm.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Qualcomm Resource Power Manager (RPM) over SMD +title: Qualcomm Resource Power Manager (RPM) over SMD/GLINK description: | This driver is used to interface with the Resource Power Manager (RPM) found @@ -12,9 +12,9 @@ description: | to vote for state of the system resources, such as clocks, regulators and bus frequencies. - The SMD information for the RPM edge should be filled out. See qcom,smd.yaml - for the required edge properties. All SMD related properties will reside - within the RPM node itself. + The SMD or GLINK information for the RPM edge should be filled out. See + qcom,smd.yaml for the required edge properties. All SMD/GLINK related + properties will reside within the RPM node itself. The RPM exposes resources to its subnodes. The rpm_requests node must be present and this subnode may contain children that designate regulator @@ -45,6 +45,7 @@ properties: - qcom,rpm-sdm660 - qcom,rpm-sm6115 - qcom,rpm-sm6125 + - qcom,rpm-sm6375 - qcom,rpm-qcm2290 - qcom,rpm-qcs404 @@ -55,12 +56,23 @@ properties: power-controller: $ref: /schemas/power/qcom,rpmpd.yaml# + qcom,glink-channels: + $ref: /schemas/types.yaml#/definitions/string-array + description: Channel name used for the RPM communication + items: + - const: rpm_requests + qcom,smd-channels: $ref: /schemas/types.yaml#/definitions/string-array description: Channel name used for the RPM communication items: - const: rpm_requests +patternProperties: + "^regulators(-[01])?$": + $ref: /schemas/regulator/qcom,smd-rpm-regulator.yaml# + unevaluatedProperties: false + if: properties: compatible: @@ -69,10 +81,18 @@ if: - qcom,rpm-apq8084 - qcom,rpm-msm8916 - qcom,rpm-msm8974 + - qcom,rpm-msm8976 - qcom,rpm-msm8953 then: + properties: + qcom,glink-channels: false required: - qcom,smd-channels +else: + properties: + qcom,smd-channels: false + required: + - qcom,glink-channels required: - compatible diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml index 795bd8cd4104..58500529b90f 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml @@ -60,7 +60,7 @@ properties: Two identifiers of the inbound and outbound smem items used for this edge. patternProperties: - "^master-kernel|slave-kernel|ipa-ap-to-modem|ipa-modem-to-ap$": + "^master-kernel|slave-kernel|ipa-ap-to-modem|ipa-modem-to-ap|wlan-ap-to-wpss|wlan-wpss-to-ap$": type: object description: Each SMP2P pair contain a set of inbound and outbound entries, these are diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml index f433e6e0a19f..38818c37c3ea 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml @@ -24,8 +24,11 @@ properties: - qcom,msm8998-silver-saw2-v4.1-l2 - qcom,msm8909-saw2-v3.0-cpu - qcom,msm8916-saw2-v3.0-cpu + - qcom,msm8939-saw2-v3.0-cpu - qcom,msm8226-saw2-v2.1-cpu - qcom,msm8974-saw2-v2.1-cpu + - qcom,msm8976-gold-saw2-v2.3-l2 + - qcom,msm8976-silver-saw2-v2.3-l2 - qcom,apq8084-saw2-v2.1-cpu - qcom,apq8064-saw2-v1.1-cpu - const: qcom,saw2 diff --git a/MAINTAINERS b/MAINTAINERS index 8f63963351b7..ca18dbfc3837 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1695,7 +1695,7 @@ M: Miquel Raynal <miquel.raynal@bootlin.com> M: Naga Sureshkumar Relli <nagasure@xilinx.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml +F: Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml F: drivers/memory/pl353-smc.c ARM PRIMECELL CLCD PL110 DRIVER @@ -12020,6 +12020,13 @@ F: drivers/*/*loongarch* F: Documentation/loongarch/ F: Documentation/translations/zh_CN/loongarch/ +LOONGSON-2 SOC SERIES GUTS DRIVER +M: Yinbo Zhu <zhuyinbo@loongson.cn> +L: loongarch@lists.linux.dev +S: Maintained +F: Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml +F: drivers/soc/loongson/loongson2_guts.c + LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) M: Sathya Prakash <sathya.prakash@broadcom.com> M: Sreekanth Reddy <sreekanth.reddy@broadcom.com> diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 41b2e8abc9e6..708816caf859 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -43,18 +43,21 @@ static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; /* - * FIXME: the timer needs some delay to stablize the counter capture + * Read the timer through the CVWR register. Delay is required after requesting + * a read. The CR register cannot be directly read due to metastability issues + * documented in the PXA168 software manual. */ static inline uint32_t timer_read(void) { - int delay = 100; + uint32_t val; + int delay = 3; __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); while (delay--) - cpu_relax(); + val = __raw_readl(mmp_timer_base + TMR_CVWR(1)); - return __raw_readl(mmp_timer_base + TMR_CVWR(1)); + return val; } static u64 notrace mmp_read_sched_clock(void) diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index 6471b559230e..a3df9b949aeb 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -494,6 +494,31 @@ void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next) } EXPORT_SYMBOL_GPL(dev_pm_genpd_set_next_wakeup); +/** + * dev_pm_genpd_get_next_hrtimer - Return the next_hrtimer for the genpd + * @dev: A device that is attached to the genpd. + * + * This routine should typically be called for a device, at the point of when a + * GENPD_NOTIFY_PRE_OFF notification has been sent for it. + * + * Returns the aggregated value of the genpd's next hrtimer or KTIME_MAX if no + * valid value have been set. + */ +ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev) +{ + struct generic_pm_domain *genpd; + + genpd = dev_to_genpd_safe(dev); + if (!genpd) + return KTIME_MAX; + + if (genpd->gd) + return genpd->gd->next_hrtimer; + + return KTIME_MAX; +} +EXPORT_SYMBOL_GPL(dev_pm_genpd_get_next_hrtimer); + static int _genpd_power_on(struct generic_pm_domain *genpd, bool timed) { unsigned int state_idx = genpd->state_idx; @@ -1994,6 +2019,7 @@ static int genpd_alloc_data(struct generic_pm_domain *genpd) gd->max_off_time_ns = -1; gd->max_off_time_changed = true; gd->next_wakeup = KTIME_MAX; + gd->next_hrtimer = KTIME_MAX; } /* Use only one "off" state if there were no states declared */ diff --git a/drivers/base/power/domain_governor.c b/drivers/base/power/domain_governor.c index 282a3a135827..cc2c3a5a6d35 100644 --- a/drivers/base/power/domain_governor.c +++ b/drivers/base/power/domain_governor.c @@ -375,6 +375,9 @@ static bool cpu_power_down_ok(struct dev_pm_domain *pd) if (idle_duration_ns <= 0) return false; + /* Store the next domain_wakeup to allow consumers to use it. */ + genpd->gd->next_hrtimer = domain_wakeup; + /* * Find the deepest idle state that has its residency value satisfied * and by also taking into account the power off latency for the state. diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c index d82a71f10c2c..0ecdffaa6b16 100644 --- a/drivers/clk/tegra/clk-bpmp.c +++ b/drivers/clk/tegra/clk-bpmp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2016-2020 NVIDIA Corporation + * Copyright (C) 2016-2022 NVIDIA Corporation */ #include <linux/clk-provider.h> @@ -310,6 +310,23 @@ static const struct clk_ops tegra_bpmp_clk_mux_rate_ops = { .set_rate = tegra_bpmp_clk_set_rate, }; +static const struct clk_ops tegra_bpmp_clk_mux_read_only_ops = { + .get_parent = tegra_bpmp_clk_get_parent, + .recalc_rate = tegra_bpmp_clk_recalc_rate, +}; + +static const struct clk_ops tegra_bpmp_clk_read_only_ops = { + .recalc_rate = tegra_bpmp_clk_recalc_rate, +}; + +static const struct clk_ops tegra_bpmp_clk_gate_mux_read_only_ops = { + .prepare = tegra_bpmp_clk_prepare, + .unprepare = tegra_bpmp_clk_unprepare, + .is_prepared = tegra_bpmp_clk_is_prepared, + .recalc_rate = tegra_bpmp_clk_recalc_rate, + .get_parent = tegra_bpmp_clk_get_parent, +}; + static int tegra_bpmp_clk_get_max_id(struct tegra_bpmp *bpmp) { struct cmd_clk_get_max_clk_id_response response; @@ -510,8 +527,22 @@ tegra_bpmp_clk_register(struct tegra_bpmp *bpmp, memset(&init, 0, sizeof(init)); init.name = info->name; clk->hw.init = &init; - - if (info->flags & TEGRA_BPMP_CLK_HAS_MUX) { + if (info->flags & BPMP_CLK_STATE_CHANGE_DENIED) { + if ((info->flags & BPMP_CLK_RATE_PARENT_CHANGE_DENIED) == 0) { + dev_WARN(bpmp->dev, + "Firmware bug! Inconsistent permission bits for clock %s. State and parent/rate changes disabled.", + init.name); + } + if (info->flags & TEGRA_BPMP_CLK_HAS_MUX) + init.ops = &tegra_bpmp_clk_mux_read_only_ops; + else + init.ops = &tegra_bpmp_clk_read_only_ops; + } else if (info->flags & BPMP_CLK_RATE_PARENT_CHANGE_DENIED) { + if (info->flags & TEGRA_BPMP_CLK_HAS_MUX) + init.ops = &tegra_bpmp_clk_gate_mux_read_only_ops; + else + init.ops = &tegra_bpmp_clk_gate_ops; + } else if (info->flags & TEGRA_BPMP_CLK_HAS_MUX) { if (info->flags & TEGRA_BPMP_CLK_HAS_SET_RATE) init.ops = &tegra_bpmp_clk_mux_rate_ops; else diff --git a/drivers/firmware/broadcom/bcm47xx_nvram.c b/drivers/firmware/broadcom/bcm47xx_nvram.c index bd235833b687..5f47dbf4889a 100644 --- a/drivers/firmware/broadcom/bcm47xx_nvram.c +++ b/drivers/firmware/broadcom/bcm47xx_nvram.c @@ -110,6 +110,24 @@ found: return 0; } +int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size) +{ + if (nvram_len) { + pr_warn("nvram already initialized\n"); + return -EEXIST; + } + + if (!bcm47xx_nvram_is_valid(nvram_start)) { + pr_err("No valid NVRAM found\n"); + return -ENOENT; + } + + bcm47xx_nvram_copy(nvram_start, res_size); + + return 0; +} +EXPORT_SYMBOL_GPL(bcm47xx_nvram_init_from_iomem); + /* * On bcm47xx we need access to the NVRAM very early, so we can't use mtd * subsystem to access flash. We can't even use platform device / driver to diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index af3d057e6421..2a4f07423365 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -108,6 +108,7 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* CONN SS */ { "usb", IMX_SC_R_USB_0, 2, true, 0 }, { "usb0phy", IMX_SC_R_USB_0_PHY, 1, false, 0 }, + { "usb1phy", IMX_SC_R_USB_1_PHY, 1, false, 0}, { "usb2", IMX_SC_R_USB_2, 1, false, 0 }, { "usb2phy", IMX_SC_R_USB_2_PHY, 1, false, 0 }, { "sdhc", IMX_SC_R_SDHC_0, 3, true, 0 }, diff --git a/drivers/firmware/raspberrypi.c b/drivers/firmware/raspberrypi.c index 4b8978b254f9..a9d7aafc6309 100644 --- a/drivers/firmware/raspberrypi.c +++ b/drivers/firmware/raspberrypi.c @@ -268,12 +268,9 @@ static int rpi_firmware_probe(struct platform_device *pdev) fw->cl.tx_block = true; fw->chan = mbox_request_channel(&fw->cl, 0); - if (IS_ERR(fw->chan)) { - int ret = PTR_ERR(fw->chan); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Failed to get mbox channel: %d\n", ret); - return ret; - } + if (IS_ERR(fw->chan)) + return dev_err_probe(dev, PTR_ERR(fw->chan), + "Failed to get mbox channel\n"); init_completion(&fw->c); kref_init(&fw->consumers); diff --git a/drivers/firmware/tegra/Kconfig b/drivers/firmware/tegra/Kconfig index 1c8ba1f47c7c..cde1ab8bd9d1 100644 --- a/drivers/firmware/tegra/Kconfig +++ b/drivers/firmware/tegra/Kconfig @@ -14,6 +14,7 @@ config TEGRA_IVC config TEGRA_BPMP bool "Tegra BPMP driver" depends on ARCH_TEGRA && TEGRA_HSP_MBOX && TEGRA_IVC + depends on !CPU_BIG_ENDIAN help BPMP (Boot and Power Management Processor) is designed to off-loading the PM functions which include clock/DVFS/thermal/power from the CPU. diff --git a/drivers/firmware/tegra/bpmp-debugfs.c b/drivers/firmware/tegra/bpmp-debugfs.c index 9d3874cdaaee..3ca2b5d9e66f 100644 --- a/drivers/firmware/tegra/bpmp-debugfs.c +++ b/drivers/firmware/tegra/bpmp-debugfs.c @@ -48,13 +48,9 @@ static int seqbuf_read(struct seqbuf *seqbuf, void *buf, size_t nbyte) return seqbuf_status(seqbuf); } -static int seqbuf_read_u32(struct seqbuf *seqbuf, uint32_t *v) +static int seqbuf_read_u32(struct seqbuf *seqbuf, u32 *v) { - int err; - - err = seqbuf_read(seqbuf, v, 4); - *v = le32_to_cpu(*v); - return err; + return seqbuf_read(seqbuf, v, 4); } static int seqbuf_read_str(struct seqbuf *seqbuf, const char **str) @@ -109,10 +105,10 @@ out: } static int mrq_debug_open(struct tegra_bpmp *bpmp, const char *name, - uint32_t *fd, uint32_t *len, bool write) + u32 *fd, u32 *len, bool write) { struct mrq_debug_request req = { - .cmd = cpu_to_le32(write ? CMD_DEBUG_OPEN_WO : CMD_DEBUG_OPEN_RO), + .cmd = write ? CMD_DEBUG_OPEN_WO : CMD_DEBUG_OPEN_RO, }; struct mrq_debug_response resp; struct tegra_bpmp_message msg = { @@ -147,10 +143,10 @@ static int mrq_debug_open(struct tegra_bpmp *bpmp, const char *name, return 0; } -static int mrq_debug_close(struct tegra_bpmp *bpmp, uint32_t fd) +static int mrq_debug_close(struct tegra_bpmp *bpmp, u32 fd) { struct mrq_debug_request req = { - .cmd = cpu_to_le32(CMD_DEBUG_CLOSE), + .cmd = CMD_DEBUG_CLOSE, .frd = { .fd = fd, }, @@ -179,10 +175,10 @@ static int mrq_debug_close(struct tegra_bpmp *bpmp, uint32_t fd) } static int mrq_debug_read(struct tegra_bpmp *bpmp, const char *name, - char *data, size_t sz_data, uint32_t *nbytes) + char *data, size_t sz_data, u32 *nbytes) { struct mrq_debug_request req = { - .cmd = cpu_to_le32(CMD_DEBUG_READ), + .cmd = CMD_DEBUG_READ, }; struct mrq_debug_response resp; struct tegra_bpmp_message msg = { @@ -196,7 +192,7 @@ static int mrq_debug_read(struct tegra_bpmp *bpmp, const char *name, .size = sizeof(resp), }, }; - uint32_t fd = 0, len = 0; + u32 fd = 0, len = 0; int remaining, err; mutex_lock(&bpmp_debug_lock); @@ -245,7 +241,7 @@ static int mrq_debug_write(struct tegra_bpmp *bpmp, const char *name, uint8_t *data, size_t sz_data) { struct mrq_debug_request req = { - .cmd = cpu_to_le32(CMD_DEBUG_WRITE) + .cmd = CMD_DEBUG_WRITE }; struct mrq_debug_response resp; struct tegra_bpmp_message msg = { @@ -259,7 +255,7 @@ static int mrq_debug_write(struct tegra_bpmp *bpmp, const char *name, .size = sizeof(resp), }, }; - uint32_t fd = 0, len = 0; + u32 fd = 0, len = 0; size_t remaining; int err; @@ -308,7 +304,7 @@ static int bpmp_debug_show(struct seq_file *m, void *p) char fnamebuf[256]; const char *filename; struct mrq_debug_request req = { - .cmd = cpu_to_le32(CMD_DEBUG_READ), + .cmd = CMD_DEBUG_READ, }; struct mrq_debug_response resp; struct tegra_bpmp_message msg = { @@ -322,7 +318,7 @@ static int bpmp_debug_show(struct seq_file *m, void *p) .size = sizeof(resp), }, }; - uint32_t fd = 0, len = 0; + u32 fd = 0, len = 0; int remaining, err; filename = get_filename(bpmp, file, fnamebuf, sizeof(fnamebuf)); @@ -406,8 +402,8 @@ static int bpmp_populate_debugfs_inband(struct tegra_bpmp *bpmp, { const size_t pathlen = SZ_256; const size_t bufsize = SZ_16K; - uint32_t dsize, attrs = 0; struct dentry *dentry; + u32 dsize, attrs = 0; struct seqbuf seqbuf; char *buf, *pathbuf; const char *name; @@ -487,12 +483,12 @@ static int mrq_debugfs_read(struct tegra_bpmp *bpmp, size_t *nbytes) { struct mrq_debugfs_request req = { - .cmd = cpu_to_le32(CMD_DEBUGFS_READ), + .cmd = CMD_DEBUGFS_READ, .fop = { - .fnameaddr = cpu_to_le32((uint32_t)name), - .fnamelen = cpu_to_le32((uint32_t)sz_name), - .dataaddr = cpu_to_le32((uint32_t)data), - .datalen = cpu_to_le32((uint32_t)sz_data), + .fnameaddr = (u32)name, + .fnamelen = (u32)sz_name, + .dataaddr = (u32)data, + .datalen = (u32)sz_data, }, }; struct mrq_debugfs_response resp; @@ -525,12 +521,12 @@ static int mrq_debugfs_write(struct tegra_bpmp *bpmp, dma_addr_t data, size_t sz_data) { const struct mrq_debugfs_request req = { - .cmd = cpu_to_le32(CMD_DEBUGFS_WRITE), + .cmd = CMD_DEBUGFS_WRITE, .fop = { - .fnameaddr = cpu_to_le32((uint32_t)name), - .fnamelen = cpu_to_le32((uint32_t)sz_name), - .dataaddr = cpu_to_le32((uint32_t)data), - .datalen = cpu_to_le32((uint32_t)sz_data), + .fnameaddr = (u32)name, + .fnamelen = (u32)sz_name, + .dataaddr = (u32)data, + .datalen = (u32)sz_data, }, }; struct tegra_bpmp_message msg = { @@ -548,10 +544,10 @@ static int mrq_debugfs_dumpdir(struct tegra_bpmp *bpmp, dma_addr_t addr, size_t size, size_t *nbytes) { const struct mrq_debugfs_request req = { - .cmd = cpu_to_le32(CMD_DEBUGFS_DUMPDIR), + .cmd = CMD_DEBUGFS_DUMPDIR, .dumpdir = { - .dataaddr = cpu_to_le32((uint32_t)addr), - .datalen = cpu_to_le32((uint32_t)size), + .dataaddr = (u32)addr, + .datalen = (u32)size, }, }; struct mrq_debugfs_response resp; @@ -688,10 +684,10 @@ static const struct file_operations debugfs_fops = { }; static int bpmp_populate_dir(struct tegra_bpmp *bpmp, struct seqbuf *seqbuf, - struct dentry *parent, uint32_t depth) + struct dentry *parent, u32 depth) { int err; - uint32_t d, t; + u32 d, t; const char *name; struct dentry *dentry; diff --git a/drivers/firmware/tegra/bpmp-tegra186.c b/drivers/firmware/tegra/bpmp-tegra186.c index 63ab21d89c2c..2e26199041cd 100644 --- a/drivers/firmware/tegra/bpmp-tegra186.c +++ b/drivers/firmware/tegra/bpmp-tegra186.c @@ -18,8 +18,8 @@ struct tegra186_bpmp { struct { struct gen_pool *pool; + void __iomem *virt; dma_addr_t phys; - void *virt; } tx, rx; struct { @@ -40,31 +40,27 @@ mbox_client_to_bpmp(struct mbox_client *client) static bool tegra186_bpmp_is_message_ready(struct tegra_bpmp_channel *channel) { - void *frame; + int err; - frame = tegra_ivc_read_get_next_frame(channel->ivc); - if (IS_ERR(frame)) { - channel->ib = NULL; + err = tegra_ivc_read_get_next_frame(channel->ivc, &channel->ib); + if (err) { + iosys_map_clear(&channel->ib); return false; } - channel->ib = frame; - return true; } static bool tegra186_bpmp_is_channel_free(struct tegra_bpmp_channel *channel) { - void *frame; + int err; - frame = tegra_ivc_write_get_next_frame(channel->ivc); - if (IS_ERR(frame)) { - channel->ob = NULL; + err = tegra_ivc_write_get_next_frame(channel->ivc, &channel->ob); + if (err) { + iosys_map_clear(&channel->ob); return false; } - channel->ob = frame; - return true; } @@ -109,6 +105,7 @@ static int tegra186_bpmp_channel_init(struct tegra_bpmp_channel *channel, { struct tegra186_bpmp *priv = bpmp->priv; size_t message_size, queue_size; + struct iosys_map rx, tx; unsigned int offset; int err; @@ -121,10 +118,11 @@ static int tegra186_bpmp_channel_init(struct tegra_bpmp_channel *channel, queue_size = tegra_ivc_total_queue_size(message_size); offset = queue_size * index; - err = tegra_ivc_init(channel->ivc, NULL, - priv->rx.virt + offset, priv->rx.phys + offset, - priv->tx.virt + offset, priv->tx.phys + offset, - 1, message_size, tegra186_bpmp_ivc_notify, + iosys_map_set_vaddr_iomem(&rx, priv->rx.virt + offset); + iosys_map_set_vaddr_iomem(&tx, priv->tx.virt + offset); + + err = tegra_ivc_init(channel->ivc, NULL, &rx, priv->rx.phys + offset, &tx, + priv->tx.phys + offset, 1, message_size, tegra186_bpmp_ivc_notify, bpmp); if (err < 0) { dev_err(bpmp->dev, "failed to setup IVC for channel %u: %d\n", @@ -179,7 +177,7 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) return -EPROBE_DEFER; } - priv->tx.virt = gen_pool_dma_alloc(priv->tx.pool, 4096, &priv->tx.phys); + priv->tx.virt = (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096, &priv->tx.phys); if (!priv->tx.virt) { dev_err(bpmp->dev, "failed to allocate from TX pool\n"); return -ENOMEM; @@ -192,7 +190,7 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) goto free_tx; } - priv->rx.virt = gen_pool_dma_alloc(priv->rx.pool, 4096, &priv->rx.phys); + priv->rx.virt = (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096, &priv->rx.phys); if (!priv->rx.virt) { dev_err(bpmp->dev, "failed to allocate from RX pool\n"); err = -ENOMEM; diff --git a/drivers/firmware/tegra/bpmp-tegra210.c b/drivers/firmware/tegra/bpmp-tegra210.c index c9c830f658c3..6295f5640c15 100644 --- a/drivers/firmware/tegra/bpmp-tegra210.c +++ b/drivers/firmware/tegra/bpmp-tegra210.c @@ -137,8 +137,8 @@ static int tegra210_bpmp_channel_init(struct tegra_bpmp_channel *channel, unsigned int index) { struct tegra210_bpmp *priv = bpmp->priv; + void __iomem *p; u32 address; - void *p; /* Retrieve channel base address from BPMP */ writel(index << TRIGGER_ID_SHIFT | TRIGGER_CMD_GET, @@ -149,8 +149,9 @@ static int tegra210_bpmp_channel_init(struct tegra_bpmp_channel *channel, if (!p) return -ENOMEM; - channel->ib = p; - channel->ob = p; + iosys_map_set_vaddr_iomem(&channel->ib, p); + iosys_map_set_vaddr_iomem(&channel->ob, p); + channel->index = index; init_completion(&channel->completion); channel->bpmp = bpmp; @@ -199,10 +200,8 @@ static int tegra210_bpmp_init(struct tegra_bpmp *bpmp) } err = platform_get_irq_byname(pdev, "tx"); - if (err < 0) { - dev_err(&pdev->dev, "failed to get TX IRQ: %d\n", err); + if (err < 0) return err; - } priv->tx_irq_data = irq_get_irq_data(err); if (!priv->tx_irq_data) { @@ -211,10 +210,8 @@ static int tegra210_bpmp_init(struct tegra_bpmp *bpmp) } err = platform_get_irq_byname(pdev, "rx"); - if (err < 0) { - dev_err(&pdev->dev, "failed to get rx IRQ: %d\n", err); + if (err < 0) return err; - } err = devm_request_irq(&pdev->dev, err, rx_irq, IRQF_NO_SUSPEND, dev_name(&pdev->dev), bpmp); diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index 037db21de510..042c2043929d 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -201,13 +201,13 @@ static ssize_t __tegra_bpmp_channel_read(struct tegra_bpmp_channel *channel, int err; if (data && size > 0) - memcpy_fromio(data, channel->ib->data, size); + tegra_bpmp_mb_read(data, &channel->ib, size); err = tegra_bpmp_ack_response(channel); if (err < 0) return err; - *ret = channel->ib->code; + *ret = tegra_bpmp_mb_read_field(&channel->ib, code); return 0; } @@ -241,11 +241,11 @@ static ssize_t __tegra_bpmp_channel_write(struct tegra_bpmp_channel *channel, unsigned int mrq, unsigned long flags, const void *data, size_t size) { - channel->ob->code = mrq; - channel->ob->flags = flags; + tegra_bpmp_mb_write_field(&channel->ob, code, mrq); + tegra_bpmp_mb_write_field(&channel->ob, flags, flags); if (data && size > 0) - memcpy_toio(channel->ob->data, data, size); + tegra_bpmp_mb_write(&channel->ob, data, size); return tegra_bpmp_post_request(channel); } @@ -400,7 +400,7 @@ static struct tegra_bpmp_mrq *tegra_bpmp_find_mrq(struct tegra_bpmp *bpmp, void tegra_bpmp_mrq_return(struct tegra_bpmp_channel *channel, int code, const void *data, size_t size) { - unsigned long flags = channel->ib->flags; + unsigned long flags = tegra_bpmp_mb_read_field(&channel->ib, flags); struct tegra_bpmp *bpmp = channel->bpmp; int err; @@ -417,10 +417,10 @@ void tegra_bpmp_mrq_return(struct tegra_bpmp_channel *channel, int code, if (WARN_ON(!tegra_bpmp_is_response_channel_free(channel))) return; - channel->ob->code = code; + tegra_bpmp_mb_write_field(&channel->ob, code, code); if (data && size > 0) - memcpy_toio(channel->ob->data, data, size); + tegra_bpmp_mb_write(&channel->ob, data, size); err = tegra_bpmp_post_response(channel); if (WARN_ON(err < 0)) @@ -502,7 +502,7 @@ EXPORT_SYMBOL_GPL(tegra_bpmp_free_mrq); bool tegra_bpmp_mrq_is_supported(struct tegra_bpmp *bpmp, unsigned int mrq) { - struct mrq_query_abi_request req = { .mrq = cpu_to_le32(mrq) }; + struct mrq_query_abi_request req = { .mrq = mrq }; struct mrq_query_abi_response resp; struct tegra_bpmp_message msg = { .mrq = MRQ_QUERY_ABI, @@ -529,13 +529,13 @@ static void tegra_bpmp_mrq_handle_ping(unsigned int mrq, struct tegra_bpmp_channel *channel, void *data) { - struct mrq_ping_request *request; + struct mrq_ping_request request; struct mrq_ping_response response; - request = (struct mrq_ping_request *)channel->ib->data; + tegra_bpmp_mb_read(&request, &channel->ib, sizeof(request)); memset(&response, 0, sizeof(response)); - response.reply = request->challenge << 1; + response.reply = request.challenge << 1; tegra_bpmp_mrq_return(channel, 0, &response, sizeof(response)); } @@ -648,7 +648,7 @@ static int tegra_bpmp_get_firmware_tag(struct tegra_bpmp *bpmp, char *tag, static void tegra_bpmp_channel_signal(struct tegra_bpmp_channel *channel) { - unsigned long flags = channel->ob->flags; + unsigned long flags = tegra_bpmp_mb_read_field(&channel->ob, flags); if ((flags & MSG_RING) == 0) return; @@ -666,8 +666,11 @@ void tegra_bpmp_handle_rx(struct tegra_bpmp *bpmp) count = bpmp->soc->channels.thread.count; busy = bpmp->threaded.busy; - if (tegra_bpmp_is_request_ready(channel)) - tegra_bpmp_handle_mrq(bpmp, channel->ib->code, channel); + if (tegra_bpmp_is_request_ready(channel)) { + unsigned int mrq = tegra_bpmp_mb_read_field(&channel->ib, code); + + tegra_bpmp_handle_mrq(bpmp, mrq, channel); + } spin_lock(&bpmp->lock); diff --git a/drivers/firmware/tegra/ivc.c b/drivers/firmware/tegra/ivc.c index e2398cd7ca98..8c9aff9804c0 100644 --- a/drivers/firmware/tegra/ivc.c +++ b/drivers/firmware/tegra/ivc.c @@ -68,6 +68,12 @@ struct tegra_ivc_header { } rx; }; +#define tegra_ivc_header_read_field(hdr, field) \ + iosys_map_rd_field(hdr, 0, struct tegra_ivc_header, field) + +#define tegra_ivc_header_write_field(hdr, field, value) \ + iosys_map_wr_field(hdr, 0, struct tegra_ivc_header, field, value) + static inline void tegra_ivc_invalidate(struct tegra_ivc *ivc, dma_addr_t phys) { if (!ivc->peer) @@ -86,16 +92,15 @@ static inline void tegra_ivc_flush(struct tegra_ivc *ivc, dma_addr_t phys) DMA_TO_DEVICE); } -static inline bool tegra_ivc_empty(struct tegra_ivc *ivc, - struct tegra_ivc_header *header) +static inline bool tegra_ivc_empty(struct tegra_ivc *ivc, struct iosys_map *map) { /* * This function performs multiple checks on the same values with * security implications, so create snapshots with READ_ONCE() to * ensure that these checks use the same values. */ - u32 tx = READ_ONCE(header->tx.count); - u32 rx = READ_ONCE(header->rx.count); + u32 tx = tegra_ivc_header_read_field(map, tx.count); + u32 rx = tegra_ivc_header_read_field(map, rx.count); /* * Perform an over-full check to prevent denial of service attacks @@ -113,11 +118,10 @@ static inline bool tegra_ivc_empty(struct tegra_ivc *ivc, return tx == rx; } -static inline bool tegra_ivc_full(struct tegra_ivc *ivc, - struct tegra_ivc_header *header) +static inline bool tegra_ivc_full(struct tegra_ivc *ivc, struct iosys_map *map) { - u32 tx = READ_ONCE(header->tx.count); - u32 rx = READ_ONCE(header->rx.count); + u32 tx = tegra_ivc_header_read_field(map, tx.count); + u32 rx = tegra_ivc_header_read_field(map, rx.count); /* * Invalid cases where the counters indicate that the queue is over @@ -126,11 +130,10 @@ static inline bool tegra_ivc_full(struct tegra_ivc *ivc, return tx - rx >= ivc->num_frames; } -static inline u32 tegra_ivc_available(struct tegra_ivc *ivc, - struct tegra_ivc_header *header) +static inline u32 tegra_ivc_available(struct tegra_ivc *ivc, struct iosys_map *map) { - u32 tx = READ_ONCE(header->tx.count); - u32 rx = READ_ONCE(header->rx.count); + u32 tx = tegra_ivc_header_read_field(map, tx.count); + u32 rx = tegra_ivc_header_read_field(map, rx.count); /* * This function isn't expected to be used in scenarios where an @@ -143,8 +146,9 @@ static inline u32 tegra_ivc_available(struct tegra_ivc *ivc, static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc) { - WRITE_ONCE(ivc->tx.channel->tx.count, - READ_ONCE(ivc->tx.channel->tx.count) + 1); + unsigned int count = tegra_ivc_header_read_field(&ivc->tx.map, tx.count); + + tegra_ivc_header_write_field(&ivc->tx.map, tx.count, count + 1); if (ivc->tx.position == ivc->num_frames - 1) ivc->tx.position = 0; @@ -154,8 +158,9 @@ static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc) static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc) { - WRITE_ONCE(ivc->rx.channel->rx.count, - READ_ONCE(ivc->rx.channel->rx.count) + 1); + unsigned int count = tegra_ivc_header_read_field(&ivc->rx.map, rx.count); + + tegra_ivc_header_write_field(&ivc->rx.map, rx.count, count + 1); if (ivc->rx.position == ivc->num_frames - 1) ivc->rx.position = 0; @@ -166,6 +171,7 @@ static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc) static inline int tegra_ivc_check_read(struct tegra_ivc *ivc) { unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); + unsigned int state; /* * tx.channel->state is set locally, so it is not synchronized with @@ -175,7 +181,8 @@ static inline int tegra_ivc_check_read(struct tegra_ivc *ivc) * asynchronous transition of rx.channel->state to * TEGRA_IVC_STATE_ACK is not allowed. */ - if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) + state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state); + if (state != TEGRA_IVC_STATE_ESTABLISHED) return -ECONNRESET; /* @@ -185,12 +192,12 @@ static inline int tegra_ivc_check_read(struct tegra_ivc *ivc) * Synchronization is only necessary when these pointers indicate * empty or full. */ - if (!tegra_ivc_empty(ivc, ivc->rx.channel)) + if (!tegra_ivc_empty(ivc, &ivc->rx.map)) return 0; tegra_ivc_invalidate(ivc, ivc->rx.phys + offset); - if (tegra_ivc_empty(ivc, ivc->rx.channel)) + if (tegra_ivc_empty(ivc, &ivc->rx.map)) return -ENOSPC; return 0; @@ -199,29 +206,34 @@ static inline int tegra_ivc_check_read(struct tegra_ivc *ivc) static inline int tegra_ivc_check_write(struct tegra_ivc *ivc) { unsigned int offset = offsetof(struct tegra_ivc_header, rx.count); + unsigned int state; - if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) + state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state); + if (state != TEGRA_IVC_STATE_ESTABLISHED) return -ECONNRESET; - if (!tegra_ivc_full(ivc, ivc->tx.channel)) + if (!tegra_ivc_full(ivc, &ivc->tx.map)) return 0; tegra_ivc_invalidate(ivc, ivc->tx.phys + offset); - if (tegra_ivc_full(ivc, ivc->tx.channel)) + if (tegra_ivc_full(ivc, &ivc->tx.map)) return -ENOSPC; return 0; } -static void *tegra_ivc_frame_virt(struct tegra_ivc *ivc, - struct tegra_ivc_header *header, - unsigned int frame) +static int tegra_ivc_frame_virt(struct tegra_ivc *ivc, const struct iosys_map *header, + unsigned int frame, struct iosys_map *map) { + size_t offset = sizeof(struct tegra_ivc_header) + ivc->frame_size * frame; + if (WARN_ON(frame >= ivc->num_frames)) - return ERR_PTR(-EINVAL); + return -EINVAL; - return (void *)(header + 1) + ivc->frame_size * frame; + *map = IOSYS_MAP_INIT_OFFSET(header, offset); + + return 0; } static inline dma_addr_t tegra_ivc_frame_phys(struct tegra_ivc *ivc, @@ -264,16 +276,16 @@ static inline void tegra_ivc_flush_frame(struct tegra_ivc *ivc, } /* directly peek at the next frame rx'ed */ -void *tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc) +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, struct iosys_map *map) { int err; if (WARN_ON(ivc == NULL)) - return ERR_PTR(-EINVAL); + return -EINVAL; err = tegra_ivc_check_read(ivc); if (err < 0) - return ERR_PTR(err); + return err; /* * Order observation of ivc->rx.position potentially indicating new @@ -284,7 +296,7 @@ void *tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc) tegra_ivc_invalidate_frame(ivc, ivc->rx.phys, ivc->rx.position, 0, ivc->frame_size); - return tegra_ivc_frame_virt(ivc, ivc->rx.channel, ivc->rx.position); + return tegra_ivc_frame_virt(ivc, &ivc->rx.map, ivc->rx.position, map); } EXPORT_SYMBOL(tegra_ivc_read_get_next_frame); @@ -320,7 +332,7 @@ int tegra_ivc_read_advance(struct tegra_ivc *ivc) */ tegra_ivc_invalidate(ivc, ivc->rx.phys + tx); - if (tegra_ivc_available(ivc, ivc->rx.channel) == ivc->num_frames - 1) + if (tegra_ivc_available(ivc, &ivc->rx.map) == ivc->num_frames - 1) ivc->notify(ivc, ivc->notify_data); return 0; @@ -328,15 +340,15 @@ int tegra_ivc_read_advance(struct tegra_ivc *ivc) EXPORT_SYMBOL(tegra_ivc_read_advance); /* directly poke at the next frame to be tx'ed */ -void *tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc) +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, struct iosys_map *map) { int err; err = tegra_ivc_check_write(ivc); if (err < 0) - return ERR_PTR(err); + return err; - return tegra_ivc_frame_virt(ivc, ivc->tx.channel, ivc->tx.position); + return tegra_ivc_frame_virt(ivc, &ivc->tx.map, ivc->tx.position, map); } EXPORT_SYMBOL(tegra_ivc_write_get_next_frame); @@ -376,7 +388,7 @@ int tegra_ivc_write_advance(struct tegra_ivc *ivc) */ tegra_ivc_invalidate(ivc, ivc->tx.phys + rx); - if (tegra_ivc_available(ivc, ivc->tx.channel) == 1) + if (tegra_ivc_available(ivc, &ivc->tx.map) == 1) ivc->notify(ivc, ivc->notify_data); return 0; @@ -387,7 +399,7 @@ void tegra_ivc_reset(struct tegra_ivc *ivc) { unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); - ivc->tx.channel->tx.state = TEGRA_IVC_STATE_SYNC; + tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_SYNC); tegra_ivc_flush(ivc, ivc->tx.phys + offset); ivc->notify(ivc, ivc->notify_data); } @@ -416,13 +428,14 @@ EXPORT_SYMBOL(tegra_ivc_reset); int tegra_ivc_notified(struct tegra_ivc *ivc) { unsigned int offset = offsetof(struct tegra_ivc_header, tx.count); - enum tegra_ivc_state state; + enum tegra_ivc_state rx_state, tx_state; /* Copy the receiver's state out of shared memory. */ tegra_ivc_invalidate(ivc, ivc->rx.phys + offset); - state = READ_ONCE(ivc->rx.channel->tx.state); + rx_state = tegra_ivc_header_read_field(&ivc->rx.map, tx.state); + tx_state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state); - if (state == TEGRA_IVC_STATE_SYNC) { + if (rx_state == TEGRA_IVC_STATE_SYNC) { offset = offsetof(struct tegra_ivc_header, tx.count); /* @@ -436,8 +449,8 @@ int tegra_ivc_notified(struct tegra_ivc *ivc) * state and won't make progress until we change our state, * so the counters are not in use at this time. */ - ivc->tx.channel->tx.count = 0; - ivc->rx.channel->rx.count = 0; + tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0); + tegra_ivc_header_write_field(&ivc->rx.map, rx.count, 0); ivc->tx.position = 0; ivc->rx.position = 0; @@ -452,7 +465,7 @@ int tegra_ivc_notified(struct tegra_ivc *ivc) * Move to ACK state. We have just cleared our counters, so it * is now safe for the remote end to start using these values. */ - ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ACK; + tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ACK); tegra_ivc_flush(ivc, ivc->tx.phys + offset); /* @@ -460,8 +473,8 @@ int tegra_ivc_notified(struct tegra_ivc *ivc) */ ivc->notify(ivc, ivc->notify_data); - } else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_SYNC && - state == TEGRA_IVC_STATE_ACK) { + } else if (tx_state == TEGRA_IVC_STATE_SYNC && + rx_state == TEGRA_IVC_STATE_ACK) { offset = offsetof(struct tegra_ivc_header, tx.count); /* @@ -475,8 +488,8 @@ int tegra_ivc_notified(struct tegra_ivc *ivc) * state and won't make progress until we change our state, * so the counters are not in use at this time. */ - ivc->tx.channel->tx.count = 0; - ivc->rx.channel->rx.count = 0; + tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0); + tegra_ivc_header_write_field(&ivc->rx.map, rx.count, 0); ivc->tx.position = 0; ivc->rx.position = 0; @@ -492,7 +505,7 @@ int tegra_ivc_notified(struct tegra_ivc *ivc) * already cleared its counters, so it is safe to start * writing/reading on this channel. */ - ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED; + tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED); tegra_ivc_flush(ivc, ivc->tx.phys + offset); /* @@ -500,7 +513,7 @@ int tegra_ivc_notified(struct tegra_ivc *ivc) */ ivc->notify(ivc, ivc->notify_data); - } else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_ACK) { + } else if (tx_state == TEGRA_IVC_STATE_ACK) { offset = offsetof(struct tegra_ivc_header, tx.count); /* @@ -516,7 +529,7 @@ int tegra_ivc_notified(struct tegra_ivc *ivc) * cleared its counters, so it is safe to start writing/reading * on this channel. */ - ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED; + tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED); tegra_ivc_flush(ivc, ivc->tx.phys + offset); /* @@ -533,7 +546,7 @@ int tegra_ivc_notified(struct tegra_ivc *ivc) */ } - if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED) + if (tx_state != TEGRA_IVC_STATE_ESTABLISHED) return -EAGAIN; return 0; @@ -609,8 +622,29 @@ static int tegra_ivc_check_params(unsigned long rx, unsigned long tx, return 0; } -int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx, - dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys, +static inline void iosys_map_copy(struct iosys_map *dst, const struct iosys_map *src) +{ + *dst = *src; +} + +static inline unsigned long iosys_map_get_address(const struct iosys_map *map) +{ + if (map->is_iomem) + return (unsigned long)map->vaddr_iomem; + + return (unsigned long)map->vaddr; +} + +static inline void *iosys_map_get_vaddr(const struct iosys_map *map) +{ + if (WARN_ON(map->is_iomem)) + return NULL; + + return map->vaddr; +} + +int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, const struct iosys_map *rx, + dma_addr_t rx_phys, const struct iosys_map *tx, dma_addr_t tx_phys, unsigned int num_frames, size_t frame_size, void (*notify)(struct tegra_ivc *ivc, void *data), void *data) @@ -628,7 +662,7 @@ int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx, if (frame_size > INT_MAX) return -E2BIG; - err = tegra_ivc_check_params((unsigned long)rx, (unsigned long)tx, + err = tegra_ivc_check_params(iosys_map_get_address(rx), iosys_map_get_address(tx), num_frames, frame_size); if (err < 0) return err; @@ -636,12 +670,12 @@ int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx, queue_size = tegra_ivc_total_queue_size(num_frames * frame_size); if (peer) { - ivc->rx.phys = dma_map_single(peer, rx, queue_size, + ivc->rx.phys = dma_map_single(peer, iosys_map_get_vaddr(rx), queue_size, DMA_BIDIRECTIONAL); if (dma_mapping_error(peer, ivc->rx.phys)) return -ENOMEM; - ivc->tx.phys = dma_map_single(peer, tx, queue_size, + ivc->tx.phys = dma_map_single(peer, iosys_map_get_vaddr(tx), queue_size, DMA_BIDIRECTIONAL); if (dma_mapping_error(peer, ivc->tx.phys)) { dma_unmap_single(peer, ivc->rx.phys, queue_size, @@ -653,8 +687,8 @@ int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx, ivc->tx.phys = tx_phys; } - ivc->rx.channel = rx; - ivc->tx.channel = tx; + iosys_map_copy(&ivc->rx.map, rx); + iosys_map_copy(&ivc->tx.map, tx); ivc->peer = peer; ivc->notify = notify; ivc->notify_data = data; diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index ebc32bbd9b83..039d92a595ec 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -429,15 +429,14 @@ static inline int ti_sci_do_xfer(struct ti_sci_info *info, * during noirq phase, so we must manually poll the completion. */ ret = read_poll_timeout_atomic(try_wait_for_completion, done_state, - true, 1, + done_state, 1, info->desc->max_rx_timeout_ms * 1000, false, &xfer->done); } - if (ret == -ETIMEDOUT || !done_state) { + if (ret == -ETIMEDOUT) dev_err(dev, "Mbox timedout in resp(caller: %pS)\n", (void *)_RET_IP_); - } /* * NOTE: we might prefer not to need the mailbox ticker to manage the @@ -3096,7 +3095,7 @@ u16 ti_sci_get_free_resource(struct ti_sci_resource *res) free_bit = find_first_zero_bit(desc->res_map, res_count); if (free_bit != res_count) { - set_bit(free_bit, desc->res_map); + __set_bit(free_bit, desc->res_map); raw_spin_unlock_irqrestore(&res->lock, flags); if (desc->num && free_bit < desc->num) @@ -3127,10 +3126,10 @@ void ti_sci_release_resource(struct ti_sci_resource *res, u16 id) if (desc->num && desc->start <= id && (desc->start + desc->num) > id) - clear_bit(id - desc->start, desc->res_map); + __clear_bit(id - desc->start, desc->res_map); else if (desc->num_sec && desc->start_sec <= id && (desc->start_sec + desc->num_sec) > id) - clear_bit(id - desc->start_sec, desc->res_map); + __clear_bit(id - desc->start_sec, desc->res_map); } raw_spin_unlock_irqrestore(&res->lock, flags); } @@ -3201,9 +3200,8 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle, valid_set = true; res_count = res->desc[i].num + res->desc[i].num_sec; - res->desc[i].res_map = - devm_kzalloc(dev, BITS_TO_LONGS(res_count) * - sizeof(*res->desc[i].res_map), GFP_KERNEL); + res->desc[i].res_map = devm_bitmap_zalloc(dev, res_count, + GFP_KERNEL); if (!res->desc[i].res_map) return ERR_PTR(-ENOMEM); } @@ -3400,13 +3398,11 @@ static int ti_sci_probe(struct platform_device *pdev) if (!minfo->xfer_block) return -ENOMEM; - minfo->xfer_alloc_table = devm_kcalloc(dev, - BITS_TO_LONGS(desc->max_msgs), - sizeof(unsigned long), - GFP_KERNEL); + minfo->xfer_alloc_table = devm_bitmap_zalloc(dev, + desc->max_msgs, + GFP_KERNEL); if (!minfo->xfer_alloc_table) return -ENOMEM; - bitmap_zero(minfo->xfer_alloc_table, desc->max_msgs); /* Pre-initialize the buffer pointer to pre-allocated buffers */ for (i = 0, xfer = minfo->xfer_block; i < desc->max_msgs; i++, xfer++) { diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c index 2351f2708da2..57d9f91fe89b 100644 --- a/drivers/memory/omap-gpmc.c +++ b/drivers/memory/omap-gpmc.c @@ -134,6 +134,7 @@ #define GPMC_CONFIG_DEV_SIZE 0x00000002 #define GPMC_CONFIG_DEV_TYPE 0x00000003 +#define GPMC_CONFIG_WAITPINPOLARITY(pin) (BIT(pin) << 8) #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) @@ -229,6 +230,12 @@ struct omap3_gpmc_regs { struct gpmc_cs_config cs_context[GPMC_CS_NUM]; }; +struct gpmc_waitpin { + u32 pin; + u32 polarity; + struct gpio_desc *desc; +}; + struct gpmc_device { struct device *dev; int irq; @@ -236,6 +243,7 @@ struct gpmc_device { struct gpio_chip gpio_chip; struct notifier_block nb; struct omap3_gpmc_regs context; + struct gpmc_waitpin *waitpins; int nirqs; unsigned int is_suspended:1; struct resource *data; @@ -1035,6 +1043,62 @@ void gpmc_cs_free(int cs) } EXPORT_SYMBOL(gpmc_cs_free); +static bool gpmc_is_valid_waitpin(u32 waitpin) +{ + return waitpin < gpmc_nr_waitpins; +} + +static int gpmc_alloc_waitpin(struct gpmc_device *gpmc, + struct gpmc_settings *p) +{ + int ret; + struct gpmc_waitpin *waitpin; + struct gpio_desc *waitpin_desc; + + if (!gpmc_is_valid_waitpin(p->wait_pin)) + return -EINVAL; + + waitpin = &gpmc->waitpins[p->wait_pin]; + + if (!waitpin->desc) { + /* Reserve the GPIO for wait pin usage. + * GPIO polarity doesn't matter here. Wait pin polarity + * is set in GPMC_CONFIG register. + */ + waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, + p->wait_pin, "WAITPIN", + GPIO_ACTIVE_HIGH, + GPIOD_IN); + + ret = PTR_ERR(waitpin_desc); + if (IS_ERR(waitpin_desc) && ret != -EBUSY) + return ret; + + /* New wait pin */ + waitpin->desc = waitpin_desc; + waitpin->pin = p->wait_pin; + waitpin->polarity = p->wait_pin_polarity; + } else { + /* Shared wait pin */ + if (p->wait_pin_polarity != waitpin->polarity || + p->wait_pin != waitpin->pin) { + dev_err(gpmc->dev, + "shared-wait-pin: invalid configuration\n"); + return -EINVAL; + } + dev_info(gpmc->dev, "shared wait-pin: %d\n", waitpin->pin); + } + + return 0; +} + +static void gpmc_free_waitpin(struct gpmc_device *gpmc, + int wait_pin) +{ + if (gpmc_is_valid_waitpin(wait_pin)) + gpiochip_free_own_desc(gpmc->waitpins[wait_pin].desc); +} + /** * gpmc_configure - write request to configure gpmc * @cmd: command type @@ -1886,6 +1950,17 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); + if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_INVALID) { + config1 = gpmc_read_reg(GPMC_CONFIG); + + if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_LOW) + config1 &= ~GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); + else if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_HIGH) + config1 |= GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); + + gpmc_write_reg(GPMC_CONFIG, config1); + } + return 0; } @@ -1975,7 +2050,25 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) __func__); } + p->wait_pin = GPMC_WAITPIN_INVALID; + p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID; + if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { + if (!gpmc_is_valid_waitpin(p->wait_pin)) { + pr_err("%s: Invalid wait-pin (%d)\n", __func__, p->wait_pin); + p->wait_pin = GPMC_WAITPIN_INVALID; + } + + if (!of_property_read_u32(np, "ti,wait-pin-polarity", + &p->wait_pin_polarity)) { + if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_HIGH && + p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_LOW) { + pr_err("%s: Invalid wait-pin-polarity (%d)\n", + __func__, p->wait_pin_polarity); + p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID; + } + } + p->wait_on_read = of_property_read_bool(np, "gpmc,wait-on-read"); p->wait_on_write = of_property_read_bool(np, @@ -2080,7 +2173,6 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, const char *name; int ret, cs; u32 val; - struct gpio_desc *waitpin_desc = NULL; struct gpmc_device *gpmc = platform_get_drvdata(pdev); if (of_property_read_u32(child, "reg", &cs) < 0) { @@ -2208,17 +2300,9 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, /* Reserve wait pin if it is required and valid */ if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) { - unsigned int wait_pin = gpmc_s.wait_pin; - - waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, - wait_pin, "WAITPIN", - GPIO_ACTIVE_HIGH, - GPIOD_IN); - if (IS_ERR(waitpin_desc)) { - dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin); - ret = PTR_ERR(waitpin_desc); + ret = gpmc_alloc_waitpin(gpmc, &gpmc_s); + if (ret < 0) goto err; - } } gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings"); @@ -2260,7 +2344,7 @@ err_child_fail: ret = -ENODEV; err_cs: - gpiochip_free_own_desc(waitpin_desc); + gpmc_free_waitpin(gpmc, gpmc_s.wait_pin); err: gpmc_cs_free(cs); @@ -2489,7 +2573,7 @@ static int omap_gpmc_context_notifier(struct notifier_block *nb, static int gpmc_probe(struct platform_device *pdev) { - int rc; + int rc, i; u32 l; struct resource *res; struct gpmc_device *gpmc; @@ -2545,6 +2629,15 @@ static int gpmc_probe(struct platform_device *pdev) gpmc_nr_waitpins = GPMC_NR_WAITPINS; } + gpmc->waitpins = devm_kzalloc(&pdev->dev, + gpmc_nr_waitpins * sizeof(struct gpmc_waitpin), + GFP_KERNEL); + if (!gpmc->waitpins) + return -ENOMEM; + + for (i = 0; i < gpmc_nr_waitpins; i++) + gpmc->waitpins[i].pin = GPMC_WAITPIN_INVALID; + pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); @@ -2598,9 +2691,12 @@ gpio_init_failed: static int gpmc_remove(struct platform_device *pdev) { + int i; struct gpmc_device *gpmc = platform_get_drvdata(pdev); cpu_pm_unregister_notifier(&gpmc->nb); + for (i = 0; i < gpmc_nr_waitpins; i++) + gpmc_free_waitpin(gpmc, i); gpmc_free_irq(gpmc); gpmc_mem_exit(); pm_runtime_put_sync(&pdev->dev); diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 4316988d791a..09cd4318a83d 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -136,7 +136,8 @@ #define RPCIF_PHYCNT_DDRCAL BIT(19) #define RPCIF_PHYCNT_HS BIT(18) #define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */ -#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */ +#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */ + #define RPCIF_PHYCNT_WBUF2 BIT(4) #define RPCIF_PHYCNT_WBUF BIT(2) #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0) @@ -317,9 +318,15 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash) regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK, RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0)); + /* DMA Transfer is not supported */ + regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0); + if (rpc->type == RPCIF_RCAR_GEN3) regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7)); + else if (rpc->type == RPCIF_RCAR_GEN4) + regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, + RPCIF_PHYCNT_STRTIM(15), RPCIF_PHYCNT_STRTIM(15)); regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3), RPCIF_PHYOFFSET1_DDRTMG(3)); @@ -330,17 +337,17 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash) regmap_update_bits(rpc->regmap, RPCIF_PHYINT, RPCIF_PHYINT_WPVAL, 0); - if (rpc->type == RPCIF_RCAR_GEN3) - regmap_update_bits(rpc->regmap, RPCIF_CMNCR, - RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3), - RPCIF_CMNCR_MOIIO(3) | - RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); - else + if (rpc->type == RPCIF_RZ_G2L) regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | RPCIF_CMNCR_BSZ(3), RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) | RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); + else + regmap_update_bits(rpc->regmap, RPCIF_CMNCR, + RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3), + RPCIF_CMNCR_MOIIO(3) | + RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); /* Set RCF after BSZ update */ regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); @@ -715,6 +722,7 @@ static int rpcif_remove(struct platform_device *pdev) static const struct of_device_id rpcif_of_match[] = { { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 }, + { .compatible = "renesas,rcar-gen4-rpc-if", .data = (void *)RPCIF_RCAR_GEN4 }, { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L }, {}, }; diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 54b47ca33483..26e763bde92a 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -84,20 +84,7 @@ static int tegra186_emc_debug_available_rates_show(struct seq_file *s, return 0; } - -static int tegra186_emc_debug_available_rates_open(struct inode *inode, - struct file *file) -{ - return single_open(file, tegra186_emc_debug_available_rates_show, - inode->i_private); -} - -static const struct file_operations tegra186_emc_debug_available_rates_fops = { - .open = tegra186_emc_debug_available_rates_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; +DEFINE_SHOW_ATTRIBUTE(tegra186_emc_debug_available_rates); static int tegra186_emc_debug_min_rate_get(void *data, u64 *rate) { diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 25ba3c5e4ad6..bd4e37b6552d 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -841,20 +841,7 @@ static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data) return 0; } - -static int tegra_emc_debug_available_rates_open(struct inode *inode, - struct file *file) -{ - return single_open(file, tegra_emc_debug_available_rates_show, - inode->i_private); -} - -static const struct file_operations tegra_emc_debug_available_rates_fops = { - .open = tegra_emc_debug_available_rates_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; +DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates); static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) { diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c index cbe1a7723514..ae5f982f861b 100644 --- a/drivers/memory/tegra/tegra210-emc-core.c +++ b/drivers/memory/tegra/tegra210-emc-core.c @@ -1621,20 +1621,7 @@ static int tegra210_emc_debug_available_rates_show(struct seq_file *s, return 0; } - -static int tegra210_emc_debug_available_rates_open(struct inode *inode, - struct file *file) -{ - return single_open(file, tegra210_emc_debug_available_rates_show, - inode->i_private); -} - -static const struct file_operations tegra210_emc_debug_available_rates_fops = { - .open = tegra210_emc_debug_available_rates_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; +DEFINE_SHOW_ATTRIBUTE(tegra210_emc_debug_available_rates); static int tegra210_emc_debug_min_rate_get(void *data, u64 *rate) { diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index a9e8fd99730f..9bdaf8af8c97 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -170,6 +170,166 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x504, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDA, + .name = "dla0rda", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x5f0, + .security = 0x5f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0FALRDB, + .name = "dla0falrdb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x5f8, + .security = 0x5fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0WRA, + .name = "dla0wra", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x600, + .security = 0x604, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, + .name = "dla0rdb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x160, + .security = 0x164, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1, + .name = "dla0rda1", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x748, + .security = 0x74c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB, + .name = "dla0falwrb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x608, + .security = 0x60c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1, + .name = "dla0rdb1", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x168, + .security = 0x16c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0WRB, + .name = "dla0wrb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x170, + .security = 0x174, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDA, + .name = "dla0rda", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x610, + .security = 0x614, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1FALRDB, + .name = "dla0falrdb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x618, + .security = 0x61c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1WRA, + .name = "dla0wra", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x620, + .security = 0x624, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDB, + .name = "dla0rdb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x178, + .security = 0x17c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1, + .name = "dla0rda1", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x750, + .security = 0x754, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB, + .name = "dla0falwrb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x628, + .security = 0x62c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, + .name = "dla0rdb1", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x370, + .security = 0x374, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1WRB, + .name = "dla0wrb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x378, + .security = 0x37c, + }, + }, }, }; diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 9ba2a9e5316b..77706e9bc543 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1359,20 +1359,7 @@ static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data) return 0; } - -static int tegra_emc_debug_available_rates_open(struct inode *inode, - struct file *file) -{ - return single_open(file, tegra_emc_debug_available_rates_show, - inode->i_private); -} - -static const struct file_operations tegra_emc_debug_available_rates_fops = { - .open = tegra_emc_debug_available_rates_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; +DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates); static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) { diff --git a/drivers/nvmem/brcm_nvram.c b/drivers/nvmem/brcm_nvram.c index 4441daa20965..34130449f2d2 100644 --- a/drivers/nvmem/brcm_nvram.c +++ b/drivers/nvmem/brcm_nvram.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */ +#include <linux/bcm47xx_nvram.h> #include <linux/io.h> #include <linux/mod_devicetable.h> #include <linux/module.h> @@ -136,6 +137,8 @@ static int brcm_nvram_probe(struct platform_device *pdev) if (err) return err; + bcm47xx_nvram_init_from_iomem(priv->base, resource_size(res)); + config.dev = dev; config.cells = priv->cells; config.ncells = priv->ncells; diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index e461c071189b..5dbb09f843f7 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -13,6 +13,7 @@ source "drivers/soc/fujitsu/Kconfig" source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" source "drivers/soc/litex/Kconfig" +source "drivers/soc/loongson/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/microchip/Kconfig" source "drivers/soc/pxa/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 69ba6508cf2c..fff513bd522d 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -18,6 +18,7 @@ obj-y += imx/ obj-y += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ +obj-y += loongson/ obj-y += mediatek/ obj-y += microchip/ obj-y += pxa/ diff --git a/drivers/soc/apple/rtkit.c b/drivers/soc/apple/rtkit.c index 031ec4aa06d5..8ec74d7539eb 100644 --- a/drivers/soc/apple/rtkit.c +++ b/drivers/soc/apple/rtkit.c @@ -926,8 +926,10 @@ int apple_rtkit_wake(struct apple_rtkit *rtk) } EXPORT_SYMBOL_GPL(apple_rtkit_wake); -static void apple_rtkit_free(struct apple_rtkit *rtk) +static void apple_rtkit_free(void *data) { + struct apple_rtkit *rtk = data; + mbox_free_channel(rtk->mbox_chan); destroy_workqueue(rtk->wq); @@ -950,8 +952,7 @@ struct apple_rtkit *devm_apple_rtkit_init(struct device *dev, void *cookie, if (IS_ERR(rtk)) return rtk; - ret = devm_add_action_or_reset(dev, (void (*)(void *))apple_rtkit_free, - rtk); + ret = devm_add_action_or_reset(dev, apple_rtkit_free, rtk); if (ret) return ERR_PTR(ret); diff --git a/drivers/soc/apple/sart.c b/drivers/soc/apple/sart.c index 83804b16ad03..afa111736899 100644 --- a/drivers/soc/apple/sart.c +++ b/drivers/soc/apple/sart.c @@ -164,6 +164,11 @@ static int apple_sart_probe(struct platform_device *pdev) return 0; } +static void apple_sart_put_device(void *dev) +{ + put_device(dev); +} + struct apple_sart *devm_apple_sart_get(struct device *dev) { struct device_node *sart_node; @@ -187,7 +192,7 @@ struct apple_sart *devm_apple_sart_get(struct device *dev) return ERR_PTR(-EPROBE_DEFER); } - ret = devm_add_action_or_reset(dev, (void (*)(void *))put_device, + ret = devm_add_action_or_reset(dev, apple_sart_put_device, &sart_pdev->dev); if (ret) return ERR_PTR(ret); diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 99f7de43c3c6..1440922341d8 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -13,10 +13,9 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/of_gpio.h> +#include <linux/of_gpio.h> /* for of_mm_gpio_chip */ +#include <linux/gpio/consumer.h> #include <linux/gpio/driver.h> -/* FIXME: needed for gpio_to_chip() get rid of this */ -#include <linux/gpio.h> #include <linux/slab.h> #include <linux/export.h> #include <soc/fsl/qe/qe.h> @@ -25,9 +24,6 @@ struct qe_gpio_chip { struct of_mm_gpio_chip mm_gc; spinlock_t lock; - unsigned long pin_flags[QE_PIO_PINS]; -#define QE_PIN_REQUESTED 0 - /* shadowed data register to clear/set bits safely */ u32 cpdata; @@ -149,62 +145,65 @@ struct qe_pin { /** * qe_pin_request - Request a QE pin - * @np: device node to get a pin from - * @index: index of a pin in the device tree + * @dev: device to get the pin from + * @index: index of the pin in the device tree * Context: non-atomic * * This function return qe_pin so that you could use it with the rest of * the QE Pin Multiplexing API. */ -struct qe_pin *qe_pin_request(struct device_node *np, int index) +struct qe_pin *qe_pin_request(struct device *dev, int index) { struct qe_pin *qe_pin; struct gpio_chip *gc; - struct qe_gpio_chip *qe_gc; + struct gpio_desc *gpiod; + int gpio_num; int err; - unsigned long flags; qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL); if (!qe_pin) { - pr_debug("%s: can't allocate memory\n", __func__); + dev_dbg(dev, "%s: can't allocate memory\n", __func__); return ERR_PTR(-ENOMEM); } - err = of_get_gpio(np, index); - if (err < 0) + /* + * Request gpio as nonexclusive as it was likely reserved by the + * caller, and we are not planning on controlling it, we only need + * the descriptor to the to the gpio chip structure. + */ + gpiod = gpiod_get_index(dev, NULL, index, + GPIOD_ASIS | GPIOD_FLAGS_BIT_NONEXCLUSIVE); + err = PTR_ERR_OR_ZERO(gpiod); + if (err) goto err0; - gc = gpio_to_chip(err); + + gc = gpiod_to_chip(gpiod); + gpio_num = desc_to_gpio(gpiod); + /* We no longer need this descriptor */ + gpiod_put(gpiod); + if (WARN_ON(!gc)) { err = -ENODEV; goto err0; } + qe_pin->controller = gpiochip_get_data(gc); + /* + * FIXME: this gets the local offset on the gpio_chip so that the driver + * can manipulate pin control settings through its custom API. The real + * solution is to create a real pin control driver for this. + */ + qe_pin->num = gpio_num - gc->base; + if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) { - pr_debug("%s: tried to get a non-qe pin\n", __func__); + dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__); err = -EINVAL; goto err0; } - - qe_gc = gpiochip_get_data(gc); - - spin_lock_irqsave(&qe_gc->lock, flags); - - err -= gc->base; - if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) { - qe_pin->controller = qe_gc; - qe_pin->num = err; - err = 0; - } else { - err = -EBUSY; - } - - spin_unlock_irqrestore(&qe_gc->lock, flags); - - if (!err) - return qe_pin; + return qe_pin; err0: kfree(qe_pin); - pr_debug("%s failed with status %d\n", __func__, err); + dev_dbg(dev, "%s failed with status %d\n", __func__, err); return ERR_PTR(err); } EXPORT_SYMBOL(qe_pin_request); @@ -219,14 +218,6 @@ EXPORT_SYMBOL(qe_pin_request); */ void qe_pin_free(struct qe_pin *qe_pin) { - struct qe_gpio_chip *qe_gc = qe_pin->controller; - unsigned long flags; - const int pin = qe_pin->num; - - spin_lock_irqsave(&qe_gc->lock, flags); - test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]); - spin_unlock_irqrestore(&qe_gc->lock, flags); - kfree(qe_pin); } EXPORT_SYMBOL(qe_pin_free); diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 88aee59730e3..7a47d14fde44 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -755,6 +755,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { [IMX8MM_POWER_DOMAIN_OTG1] = { .genpd = { .name = "usb-otg1", + .flags = GENPD_FLAG_ACTIVE_WAKEUP, }, .bits = { .pxx = IMX8MM_OTG1_SW_Pxx_REQ, @@ -766,6 +767,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { [IMX8MM_POWER_DOMAIN_OTG2] = { .genpd = { .name = "usb-otg2", + .flags = GENPD_FLAG_ACTIVE_WAKEUP, }, .bits = { .pxx = IMX8MM_OTG2_SW_Pxx_REQ, @@ -1232,6 +1234,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { [IMX8MN_POWER_DOMAIN_OTG1] = { .genpd = { .name = "usb-otg1", + .flags = GENPD_FLAG_ACTIVE_WAKEUP, }, .bits = { .pxx = IMX8MN_OTG1_SW_Pxx_REQ, diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 00879615a701..ddcf6be3d8b4 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -210,9 +210,14 @@ static int imx8m_blk_ctrl_probe(struct platform_device *pdev) return -ENOMEM; bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus"); - if (IS_ERR(bc->bus_power_dev)) - return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev), - "failed to attach power domain \"bus\"\n"); + if (IS_ERR(bc->bus_power_dev)) { + if (PTR_ERR(bc->bus_power_dev) == -ENODEV) + return dev_err_probe(dev, -EPROBE_DEFER, + "failed to attach power domain \"bus\"\n"); + else + return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev), + "failed to attach power domain \"bus\"\n"); + } for (i = 0; i < bc_data->num_domains; i++) { const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i]; diff --git a/drivers/soc/loongson/Kconfig b/drivers/soc/loongson/Kconfig new file mode 100644 index 000000000000..707f56358dc4 --- /dev/null +++ b/drivers/soc/loongson/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Loongson-2 series SoC drivers +# + +config LOONGSON2_GUTS + tristate "Loongson-2 SoC Global UtiliTieS (GUTS) register block" + depends on LOONGARCH || COMPILE_TEST + select SOC_BUS + help + The global utilities block controls PCIE device enabling, alternate + function selection for multiplexed signals, consistency of HDA, USB + and PCIE, configuration of memory controller, rtc controller, lio + controller, and clock control. This patch adds a driver to manage + and access global utilities block for LoongArch architecture Loongson-2 + SoCs. Initially only reading SVR and registering soc device are + supported. Other guts accesses, such as reading firmware configuration + by default, should eventually be added into this driver as well. diff --git a/drivers/soc/loongson/Makefile b/drivers/soc/loongson/Makefile new file mode 100644 index 000000000000..263c486df638 --- /dev/null +++ b/drivers/soc/loongson/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile for the Linux Kernel SoC Loongson-2 specific device drivers +# + +obj-$(CONFIG_LOONGSON2_GUTS) += loongson2_guts.o diff --git a/drivers/soc/loongson/loongson2_guts.c b/drivers/soc/loongson/loongson2_guts.c new file mode 100644 index 000000000000..bace4bc8e03b --- /dev/null +++ b/drivers/soc/loongson/loongson2_guts.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: Yinbo Zhu <zhuyinbo@loongson.cn> + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited + */ + +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/of_fdt.h> +#include <linux/sys_soc.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +static struct soc_device_attribute soc_dev_attr; +static struct soc_device *soc_dev; + +/* + * Global Utility Registers. + * + * Not all registers defined in this structure are available on all chips, so + * you are expected to know whether a given register actually exists on your + * chip before you access it. + * + * Also, some registers are similar on different chips but have slightly + * different names. In these cases, one name is chosen to avoid extraneous + * #ifdefs. + */ +struct scfg_guts { + u32 svr; /* Version Register */ + u8 res0[4]; + u16 feature; /* Feature Register */ + u32 vendor; /* Vendor Register */ + u8 res1[6]; + u32 id; + u8 res2[0x3ff8 - 0x18]; + u32 chip; +}; + +static struct guts { + struct scfg_guts __iomem *regs; + bool little_endian; +} *guts; + +struct loongson2_soc_die_attr { + char *die; + u32 svr; + u32 mask; +}; + +/* SoC die attribute definition for Loongson-2 platform */ +static const struct loongson2_soc_die_attr loongson2_soc_die[] = { + + /* + * LoongArch-based SoCs Loongson-2 Series + */ + + /* Die: 2k1000, SoC: 2k1000 */ + { .die = "2K1000", + .svr = 0x00000013, + .mask = 0x000000ff, + }, + { }, +}; + +static const struct loongson2_soc_die_attr *loongson2_soc_die_match( + u32 svr, const struct loongson2_soc_die_attr *matches) +{ + while (matches->svr) { + if (matches->svr == (svr & matches->mask)) + return matches; + matches++; + }; + + return NULL; +} + +static u32 loongson2_guts_get_svr(void) +{ + u32 svr = 0; + + if (!guts || !guts->regs) + return svr; + + if (guts->little_endian) + svr = ioread32(&guts->regs->svr); + else + svr = ioread32be(&guts->regs->svr); + + return svr; +} + +static int loongson2_guts_probe(struct platform_device *pdev) +{ + struct device_node *root, *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct resource *res; + const struct loongson2_soc_die_attr *soc_die; + const char *machine; + u32 svr; + + /* Initialize guts */ + guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL); + if (!guts) + return -ENOMEM; + + guts->little_endian = of_property_read_bool(np, "little-endian"); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + guts->regs = ioremap(res->start, res->end - res->start + 1); + if (IS_ERR(guts->regs)) + return PTR_ERR(guts->regs); + + /* Register soc device */ + root = of_find_node_by_path("/"); + if (of_property_read_string(root, "model", &machine)) + of_property_read_string_index(root, "compatible", 0, &machine); + of_node_put(root); + if (machine) + soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL); + + svr = loongson2_guts_get_svr(); + soc_die = loongson2_soc_die_match(svr, loongson2_soc_die); + if (soc_die) { + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, + "Loongson %s", soc_die->die); + } else { + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "Loongson"); + } + if (!soc_dev_attr.family) + return -ENOMEM; + soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL, + "svr:0x%08x", svr); + if (!soc_dev_attr.soc_id) + return -ENOMEM; + soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d", + (svr >> 4) & 0xf, svr & 0xf); + if (!soc_dev_attr.revision) + return -ENOMEM; + + soc_dev = soc_device_register(&soc_dev_attr); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + pr_info("Machine: %s\n", soc_dev_attr.machine); + pr_info("SoC family: %s\n", soc_dev_attr.family); + pr_info("SoC ID: %s, Revision: %s\n", + soc_dev_attr.soc_id, soc_dev_attr.revision); + + return 0; +} + +static int loongson2_guts_remove(struct platform_device *dev) +{ + soc_device_unregister(soc_dev); + + return 0; +} + +/* + * Table for matching compatible strings, for device tree + * guts node, for Loongson-2 SoCs. + */ +static const struct of_device_id loongson2_guts_of_match[] = { + { .compatible = "loongson,ls2k-chipid", }, + {} +}; +MODULE_DEVICE_TABLE(of, loongson2_guts_of_match); + +static struct platform_driver loongson2_guts_driver = { + .driver = { + .name = "loongson2-guts", + .of_match_table = loongson2_guts_of_match, + }, + .probe = loongson2_guts_probe, + .remove = loongson2_guts_remove, +}; + +static int __init loongson2_guts_init(void) +{ + return platform_driver_register(&loongson2_guts_driver); +} +core_initcall(loongson2_guts_init); + +static void __exit loongson2_guts_exit(void) +{ + platform_driver_unregister(&loongson2_guts_driver); +} +module_exit(loongson2_guts_exit); + +MODULE_DESCRIPTION("Loongson2 GUTS driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h index 09b1ccbc0093..279d4138525b 100644 --- a/drivers/soc/mediatek/mt8186-mmsys.h +++ b/drivers/soc/mediatek/mt8186-mmsys.h @@ -5,9 +5,11 @@ /* Values for DPI configuration in MMSYS address space */ #define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400 -#define DPI_FORMAT_MASK 0x1 -#define DPI_RGB888_DDR_CON BIT(0) -#define DPI_RGB565_SDR_CON BIT(1) +#define MT8186_DPI_FORMAT_MASK GENMASK(1, 0) +#define MT8186_DPI_RGB888_SDR_CON 0 +#define MT8186_DPI_RGB888_DDR_CON 1 +#define MT8186_DPI_RGB565_SDR_CON 2 +#define MT8186_DPI_RGB565_DDR_CON 3 #define MT8186_MMSYS_OVL_CON 0xF04 #define MT8186_MMSYS_OVL0_CON_MASK 0x3 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index d2c7a87aab87..f3431448e843 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -26,61 +26,26 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mmsys_default_routing_table), }; -static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt2701_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), }; -static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt2712_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", }; -static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt6779_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", }; -static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt6797_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .clk_driver = "clk-mt8167-mm", .routes = mt8167_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), }; -static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8167_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", .routes = mmsys_default_routing_table, @@ -88,13 +53,6 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, }; -static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8173_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .routes = mmsys_mt8183_routing_table, @@ -102,13 +60,6 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, }; -static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8183_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .clk_driver = "clk-mt8186-mm", .routes = mmsys_mt8186_routing_table, @@ -116,13 +67,6 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; -static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8186_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, @@ -130,66 +74,25 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; -static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8192_mmsys_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { - .io_start = 0x1c01a000, .clk_driver = "clk-mt8195-vdo0", .routes = mmsys_mt8195_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), }; -static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { - .io_start = 0x1c100000, - .clk_driver = "clk-mt8195-vdo1", -}; - -static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = { - .num_drv_data = 2, - .drv_data = { - &mt8195_vdosys0_driver_data, - &mt8195_vdosys1_driver_data, - }, -}; - static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .clk_driver = "clk-mt8365-mm", .routes = mt8365_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), }; -static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = { - .num_drv_data = 1, - .drv_data = { - &mt8365_mmsys_driver_data, - }, -}; - struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; - phys_addr_t io_start; }; -static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys, - const struct mtk_mmsys_match_data *match) -{ - int i; - - for (i = 0; i < match->num_drv_data; i++) - if (mmsys->io_start == match->drv_data[i]->io_start) - return i; - - return -EINVAL; -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) @@ -238,12 +141,27 @@ static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) { - if (val) - mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8186_MMSYS_DPI_OUTPUT_FORMAT, - DPI_RGB888_DDR_CON, DPI_FORMAT_MASK); - else - mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8186_MMSYS_DPI_OUTPUT_FORMAT, - DPI_RGB565_SDR_CON, DPI_FORMAT_MASK); + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + + switch (val) { + case MTK_DPI_RGB888_SDR_CON: + mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, + MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON); + break; + case MTK_DPI_RGB565_SDR_CON: + mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, + MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON); + break; + case MTK_DPI_RGB565_DDR_CON: + mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, + MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON); + break; + case MTK_DPI_RGB888_DDR_CON: + default: + mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, + MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON); + break; + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config); @@ -304,9 +222,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct platform_device *clks; struct platform_device *drm; - const struct mtk_mmsys_match_data *match_data; struct mtk_mmsys *mmsys; - struct resource *res; int ret; mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); @@ -332,27 +248,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "Couldn't get mmsys resource\n"); - return -EINVAL; - } - mmsys->io_start = res->start; - - match_data = of_device_get_match_data(dev); - if (match_data->num_drv_data > 1) { - /* This SoC has multiple mmsys channels */ - ret = mtk_mmsys_find_match_drvdata(mmsys, match_data); - if (ret < 0) { - dev_err(dev, "Couldn't get match driver data\n"); - return ret; - } - mmsys->data = match_data->drv_data[ret]; - } else { - dev_dbg(dev, "Using single mmsys channel\n"); - mmsys->data = match_data->drv_data[0]; - } - + mmsys->data = of_device_get_match_data(&pdev->dev); platform_set_drvdata(pdev, mmsys); clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, @@ -373,47 +269,51 @@ static int mtk_mmsys_probe(struct platform_device *pdev) static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_match_data, + .data = &mt2701_mmsys_driver_data, }, { .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_match_data, + .data = &mt2712_mmsys_driver_data, }, { .compatible = "mediatek,mt6779-mmsys", - .data = &mt6779_mmsys_match_data, + .data = &mt6779_mmsys_driver_data, }, { .compatible = "mediatek,mt6797-mmsys", - .data = &mt6797_mmsys_match_data, + .data = &mt6797_mmsys_driver_data, }, { .compatible = "mediatek,mt8167-mmsys", - .data = &mt8167_mmsys_match_data, + .data = &mt8167_mmsys_driver_data, }, { .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_match_data, + .data = &mt8173_mmsys_driver_data, }, { .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_match_data, + .data = &mt8183_mmsys_driver_data, }, { .compatible = "mediatek,mt8186-mmsys", - .data = &mt8186_mmsys_match_data, + .data = &mt8186_mmsys_driver_data, }, { .compatible = "mediatek,mt8192-mmsys", - .data = &mt8192_mmsys_match_data, + .data = &mt8192_mmsys_driver_data, }, - { + { /* deprecated compatible */ .compatible = "mediatek,mt8195-mmsys", - .data = &mt8195_mmsys_match_data, + .data = &mt8195_vdosys0_driver_data, + }, + { + .compatible = "mediatek,mt8195-vdosys0", + .data = &mt8195_vdosys0_driver_data, }, { .compatible = "mediatek,mt8365-mmsys", - .data = &mt8365_mmsys_match_data, + .data = &mt8365_mmsys_driver_data, }, { } }; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index f01ba206481d..77f37f8c715b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -87,18 +87,12 @@ struct mtk_mmsys_routes { }; struct mtk_mmsys_driver_data { - const resource_size_t io_start; const char *clk_driver; const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; }; -struct mtk_mmsys_match_data { - unsigned short num_drv_data; - const struct mtk_mmsys_driver_data *drv_data[]; -}; - /* * Routes in mt8173, mt2701, mt2712 are different. That means * in the same register address, it controls different input/output diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index eb82ae06697f..15789a03e6c6 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -983,6 +983,68 @@ static int mt8195_regs[] = { [PWRAP_WACS2_RDATA] = 0x8A8, }; +static int mt8365_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_CSHEXT_WRITE] = 0x24, + [PWRAP_CSHEXT_READ] = 0x28, + [PWRAP_STAUPD_PRD] = 0x3c, + [PWRAP_STAUPD_GRPEN] = 0x40, + [PWRAP_STAUPD_MAN_TRIG] = 0x58, + [PWRAP_STAUPD_STA] = 0x5c, + [PWRAP_WRAP_STA] = 0x60, + [PWRAP_HARB_INIT] = 0x64, + [PWRAP_HARB_HPRIO] = 0x68, + [PWRAP_HIPRIO_ARB_EN] = 0x6c, + [PWRAP_HARB_STA0] = 0x70, + [PWRAP_HARB_STA1] = 0x74, + [PWRAP_MAN_EN] = 0x7c, + [PWRAP_MAN_CMD] = 0x80, + [PWRAP_MAN_RDATA] = 0x84, + [PWRAP_MAN_VLDCLR] = 0x88, + [PWRAP_WACS0_EN] = 0x8c, + [PWRAP_INIT_DONE0] = 0x90, + [PWRAP_WACS0_CMD] = 0xc00, + [PWRAP_WACS0_RDATA] = 0xc04, + [PWRAP_WACS0_VLDCLR] = 0xc08, + [PWRAP_WACS1_EN] = 0x94, + [PWRAP_INIT_DONE1] = 0x98, + [PWRAP_WACS2_EN] = 0x9c, + [PWRAP_INIT_DONE2] = 0xa0, + [PWRAP_WACS2_CMD] = 0xc20, + [PWRAP_WACS2_RDATA] = 0xc24, + [PWRAP_WACS2_VLDCLR] = 0xc28, + [PWRAP_INT_EN] = 0xb4, + [PWRAP_INT_FLG_RAW] = 0xb8, + [PWRAP_INT_FLG] = 0xbc, + [PWRAP_INT_CLR] = 0xc0, + [PWRAP_SIG_ADR] = 0xd4, + [PWRAP_SIG_MODE] = 0xd8, + [PWRAP_SIG_VALUE] = 0xdc, + [PWRAP_SIG_ERRVAL] = 0xe0, + [PWRAP_CRC_EN] = 0xe4, + [PWRAP_TIMER_EN] = 0xe8, + [PWRAP_TIMER_STA] = 0xec, + [PWRAP_WDT_UNIT] = 0xf0, + [PWRAP_WDT_SRC_EN] = 0xf4, + [PWRAP_WDT_FLG] = 0xfc, + [PWRAP_DEBUG_INT_SEL] = 0x104, + [PWRAP_CIPHER_KEY_SEL] = 0x1c4, + [PWRAP_CIPHER_IV_SEL] = 0x1c8, + [PWRAP_CIPHER_RDY] = 0x1d0, + [PWRAP_CIPHER_MODE] = 0x1d4, + [PWRAP_CIPHER_SWRST] = 0x1d8, + [PWRAP_DCM_EN] = 0x1dc, + [PWRAP_DCM_DBC_PRD] = 0x1e0, + [PWRAP_EINT_STA0_ADR] = 0x44, + [PWRAP_EINT_STA1_ADR] = 0x48, + [PWRAP_INT1_EN] = 0xc4, + [PWRAP_INT1_FLG] = 0xcc, + [PWRAP_INT1_CLR] = 0xd0, + [PWRAP_WDT_SRC_EN_1] = 0xf8, +}; + static int mt8516_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1139,6 +1201,7 @@ enum pwrap_type { PWRAP_MT8183, PWRAP_MT8186, PWRAP_MT8195, + PWRAP_MT8365, PWRAP_MT8516, }; @@ -1171,6 +1234,8 @@ struct pmic_wrapper { const struct pwrap_slv_type *slave; struct clk *clk_spi; struct clk *clk_wrap; + struct clk *clk_sys; + struct clk *clk_tmr; struct reset_control *rstc; struct reset_control *rstc_bridge; @@ -1596,6 +1661,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT6797: case PWRAP_MT8173: case PWRAP_MT8186: + case PWRAP_MT8365: case PWRAP_MT8516: pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); break; @@ -2104,6 +2170,19 @@ static struct pmic_wrapper_type pwrap_mt8195 = { .init_soc_specific = NULL, }; +static const struct pmic_wrapper_type pwrap_mt8365 = { + .regs = mt8365_regs, + .type = PWRAP_MT8365, + .arb_en_all = 0x3ffff, + .int_en_all = 0x7f1fffff, + .int1_en_all = 0x0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = NULL, +}; + static struct pmic_wrapper_type pwrap_mt8516 = { .regs = mt8516_regs, .type = PWRAP_MT8516, @@ -2141,6 +2220,7 @@ static const struct of_device_id of_pwrap_match_tbl[] = { { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 }, { .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 }, { .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195 }, + { .compatible = "mediatek,mt8365-pwrap", .data = &pwrap_mt8365 }, { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516 }, { /* sentinel */ } }; @@ -2214,6 +2294,20 @@ static int pwrap_probe(struct platform_device *pdev) return PTR_ERR(wrp->clk_wrap); } + wrp->clk_sys = devm_clk_get_optional(wrp->dev, "sys"); + if (IS_ERR(wrp->clk_sys)) { + return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_sys), + "failed to get clock: %pe\n", + wrp->clk_sys); + } + + wrp->clk_tmr = devm_clk_get_optional(wrp->dev, "tmr"); + if (IS_ERR(wrp->clk_tmr)) { + return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_tmr), + "failed to get clock: %pe\n", + wrp->clk_tmr); + } + ret = clk_prepare_enable(wrp->clk_spi); if (ret) return ret; @@ -2222,6 +2316,14 @@ static int pwrap_probe(struct platform_device *pdev) if (ret) goto err_out1; + ret = clk_prepare_enable(wrp->clk_sys); + if (ret) + goto err_out2; + + ret = clk_prepare_enable(wrp->clk_tmr); + if (ret) + goto err_out3; + /* Enable internal dynamic clock */ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) { pwrap_writel(wrp, 1, PWRAP_DCM_EN); @@ -2236,7 +2338,7 @@ static int pwrap_probe(struct platform_device *pdev) ret = pwrap_init(wrp); if (ret) { dev_dbg(wrp->dev, "init failed with %d\n", ret); - goto err_out2; + goto err_out4; } } @@ -2250,7 +2352,7 @@ static int pwrap_probe(struct platform_device *pdev) if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) { dev_dbg(wrp->dev, "initialization isn't finished\n"); ret = -ENODEV; - goto err_out2; + goto err_out4; } /* Initialize watchdog, may not be done by the bootloader */ @@ -2288,7 +2390,7 @@ static int pwrap_probe(struct platform_device *pdev) IRQF_TRIGGER_HIGH, "mt-pmic-pwrap", wrp); if (ret) - goto err_out2; + goto err_out4; wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops->regmap); if (IS_ERR(wrp->regmap)) { @@ -2300,11 +2402,15 @@ static int pwrap_probe(struct platform_device *pdev) if (ret) { dev_dbg(wrp->dev, "failed to create child devices at %pOF\n", np); - goto err_out2; + goto err_out4; } return 0; +err_out4: + clk_disable_unprepare(wrp->clk_tmr); +err_out3: + clk_disable_unprepare(wrp->clk_sys); err_out2: clk_disable_unprepare(wrp->clk_wrap); err_out1: diff --git a/drivers/soc/pxa/ssp.c b/drivers/soc/pxa/ssp.c index 93449fb3519e..bd029e838241 100644 --- a/drivers/soc/pxa/ssp.c +++ b/drivers/soc/pxa/ssp.c @@ -146,10 +146,8 @@ static int pxa_ssp_probe(struct platform_device *pdev) } ssp->irq = platform_get_irq(pdev, 0); - if (ssp->irq < 0) { - dev_err(dev, "no IRQ resource defined\n"); + if (ssp->irq < 0) return -ENODEV; - } if (dev->of_node) { const struct of_device_id *id = diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 024e420f1bb7..ae504c43d9e7 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -63,6 +63,7 @@ config QCOM_GSBI config QCOM_LLCC tristate "Qualcomm Technologies, Inc. LLCC driver" depends on ARCH_QCOM || COMPILE_TEST + select REGMAP_MMIO help Qualcomm Technologies, Inc. platform specific Last Level Cache Controller(LLCC) driver for platforms such as, @@ -236,6 +237,7 @@ config QCOM_ICC_BWMON tristate "QCOM Interconnect Bandwidth Monitor driver" depends on ARCH_QCOM || COMPILE_TEST select PM_OPP + select REGMAP_MMIO help Sets up driver monitoring bandwidth on various interconnects and based on that voting for interconnect bandwidth, adjusting their diff --git a/drivers/soc/qcom/apr.c b/drivers/soc/qcom/apr.c index b4046f393575..cd44f17dad3d 100644 --- a/drivers/soc/qcom/apr.c +++ b/drivers/soc/qcom/apr.c @@ -454,11 +454,19 @@ static int apr_add_device(struct device *dev, struct device_node *np, adev->dev.driver = NULL; spin_lock(&apr->svcs_lock); - idr_alloc(&apr->svcs_idr, svc, svc_id, svc_id + 1, GFP_ATOMIC); + ret = idr_alloc(&apr->svcs_idr, svc, svc_id, svc_id + 1, GFP_ATOMIC); spin_unlock(&apr->svcs_lock); + if (ret < 0) { + dev_err(dev, "idr_alloc failed: %d\n", ret); + goto out; + } - of_property_read_string_index(np, "qcom,protection-domain", - 1, &adev->service_path); + ret = of_property_read_string_index(np, "qcom,protection-domain", + 1, &adev->service_path); + if (ret < 0) { + dev_err(dev, "Failed to read second value of qcom,protection-domain\n"); + goto out; + } dev_info(dev, "Adding APR/GPR dev: %s\n", dev_name(&adev->dev)); @@ -468,6 +476,7 @@ static int apr_add_device(struct device *dev, struct device_node *np, put_device(&adev->dev); } +out: return ret; } diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c index 629a7188b576..33856abd560c 100644 --- a/drivers/soc/qcom/cmd-db.c +++ b/drivers/soc/qcom/cmd-db.c @@ -338,6 +338,8 @@ static int cmd_db_dev_probe(struct platform_device *pdev) debugfs_create_file("cmd-db", 0400, NULL, NULL, &cmd_db_debugfs_ops); + device_set_pm_not_required(&pdev->dev); + return 0; } diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 8b7e8118f3ce..23ce2f78c4ed 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -21,6 +21,8 @@ #define ACTIVATE BIT(0) #define DEACTIVATE BIT(1) +#define ACT_CLEAR BIT(0) +#define ACT_COMPLETE BIT(4) #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) #define ACT_CTRL_ACT_TRIG BIT(0) @@ -41,19 +43,30 @@ #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) +#define LLCC_TRP_ACT_CLEARn(n) (8 + n * SZ_4K) #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) +#define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_8 * n) #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 #define LLCC_TRP_PCB_ACT 0x21f04 +#define LLCC_TRP_ALGO_CFG1 0x21f0c +#define LLCC_TRP_ALGO_CFG2 0x21f10 +#define LLCC_TRP_ALGO_CFG3 0x21f14 +#define LLCC_TRP_ALGO_CFG4 0x21f18 +#define LLCC_TRP_ALGO_CFG5 0x21f1c #define LLCC_TRP_WRSC_EN 0x21f20 +#define LLCC_TRP_ALGO_CFG6 0x21f24 +#define LLCC_TRP_ALGO_CFG7 0x21f28 #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c +#define LLCC_TRP_ALGO_CFG8 0x21f30 #define BANK_OFFSET_STRIDE 0x80000 #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 +#define LLCC_VERSION_4_1_0_0 0x04010000 /** * struct llcc_slice_config - Data associated with the llcc slice @@ -97,6 +110,14 @@ struct llcc_slice_config { bool activate_on_init; bool write_scid_en; bool write_scid_cacheable_en; + bool stale_en; + bool stale_cap_en; + bool mru_uncap_en; + bool mru_rollover; + bool alloc_oneway_en; + bool ovcap_en; + bool ovcap_prio; + bool vict_prio; }; struct qcom_llcc_config { @@ -297,6 +318,38 @@ static const struct llcc_slice_config sm8450_data[] = { {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, }; +static const struct llcc_slice_config sm8550_data[] = { + {LLCC_CPUSS, 1, 5120, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_VIDSC0, 2, 512, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_MDMHPGRW, 25, 1024, 4, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_MODHW, 26, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_GPU, 9, 3096, 1, 0, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_MMUHWT, 18, 768, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_DISP, 16, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_MDMPNG, 27, 1024, 0, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_CVP, 8, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_MODPE, 29, 64, 1, 1, 0xF00000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, }, + {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_CAMEXP0, 4, 256, 4, 1, 0xF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_CAMEXP1, 7, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_CMPTHCP, 17, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_LCPDARE, 30, 128, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, }, + {LLCC_AENPU, 3, 3072, 1, 1, 0xFE01FF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_ISLAND1, 12, 1792, 7, 1, 0xFE00, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_ISLAND4, 15, 256, 7, 1, 0x10000, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_CAMEXP2, 19, 3200, 3, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_CAMEXP3, 20, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_CAMEXP4, 21, 3200, 2, 1, 0xFFFFF0, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_DISP_WB, 23, 1024, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_DISP_1, 24, 6144, 1, 1, 0xFFFFFF, 0x0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, +}; + static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = { .trp_ecc_error_status0 = 0x20344, .trp_ecc_error_status1 = 0x20348, @@ -443,6 +496,14 @@ static const struct qcom_llcc_config sm8450_cfg = { .edac_reg_offset = &llcc_v2_1_edac_reg_offset, }; +static const struct qcom_llcc_config sm8550_cfg = { + .sct_data = sm8550_data, + .size = ARRAY_SIZE(sm8550_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, +}; + static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; /** @@ -497,6 +558,7 @@ static int llcc_update_act_ctrl(u32 sid, u32 act_ctrl_reg_val, u32 status) { u32 act_ctrl_reg; + u32 act_clear_reg; u32 status_reg; u32 slice_status; int ret; @@ -505,6 +567,7 @@ static int llcc_update_act_ctrl(u32 sid, return PTR_ERR(drv_data); act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); + act_clear_reg = LLCC_TRP_ACT_CLEARn(sid); status_reg = LLCC_TRP_STATUSn(sid); /* Set the ACTIVE trigger */ @@ -521,9 +584,22 @@ static int llcc_update_act_ctrl(u32 sid, if (ret) return ret; + if (drv_data->version >= LLCC_VERSION_4_1_0_0) { + ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, + slice_status, (slice_status & ACT_COMPLETE), + 0, LLCC_STATUS_READ_DELAY); + if (ret) + return ret; + } + ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, slice_status, !(slice_status & status), 0, LLCC_STATUS_READ_DELAY); + + if (drv_data->version >= LLCC_VERSION_4_1_0_0) + ret = regmap_write(drv_data->bcast_regmap, act_clear_reg, + ACT_CLEAR); + return ret; } @@ -636,8 +712,10 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, const struct qcom_llcc_config *cfg) { int ret; + u32 attr2_cfg; u32 attr1_cfg; u32 attr0_cfg; + u32 attr2_val; u32 attr1_val; u32 attr0_val; u32 max_cap_cacheline; @@ -667,8 +745,14 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, if (ret) return ret; - attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; - attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; + if (drv_data->version >= LLCC_VERSION_4_1_0_0) { + attr2_cfg = LLCC_TRP_ATTR2_CFGn(config->slice_id); + attr0_val = config->res_ways; + attr2_val = config->bonus_ways; + } else { + attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; + attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; + } attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); @@ -676,6 +760,12 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, if (ret) return ret; + if (drv_data->version >= LLCC_VERSION_4_1_0_0) { + ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val); + if (ret) + return ret; + } + if (cfg->need_llcc_cfg) { u32 disable_cap_alloc, retain_pc; @@ -685,11 +775,13 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, if (ret) return ret; - retain_pc = config->retain_on_pc << config->slice_id; - ret = regmap_write(drv_data->bcast_regmap, - LLCC_TRP_PCB_ACT, retain_pc); - if (ret) - return ret; + if (drv_data->version < LLCC_VERSION_4_1_0_0) { + retain_pc = config->retain_on_pc << config->slice_id; + ret = regmap_write(drv_data->bcast_regmap, + LLCC_TRP_PCB_ACT, retain_pc); + if (ret) + return ret; + } } if (drv_data->version >= LLCC_VERSION_2_0_0_0) { @@ -712,6 +804,65 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, return ret; } + if (drv_data->version >= LLCC_VERSION_4_1_0_0) { + u32 stale_en; + u32 stale_cap_en; + u32 mru_uncap_en; + u32 mru_rollover; + u32 alloc_oneway_en; + u32 ovcap_en; + u32 ovcap_prio; + u32 vict_prio; + + stale_en = config->stale_en << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG1, + BIT(config->slice_id), stale_en); + if (ret) + return ret; + + stale_cap_en = config->stale_cap_en << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG2, + BIT(config->slice_id), stale_cap_en); + if (ret) + return ret; + + mru_uncap_en = config->mru_uncap_en << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG3, + BIT(config->slice_id), mru_uncap_en); + if (ret) + return ret; + + mru_rollover = config->mru_rollover << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG4, + BIT(config->slice_id), mru_rollover); + if (ret) + return ret; + + alloc_oneway_en = config->alloc_oneway_en << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG5, + BIT(config->slice_id), alloc_oneway_en); + if (ret) + return ret; + + ovcap_en = config->ovcap_en << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG6, + BIT(config->slice_id), ovcap_en); + if (ret) + return ret; + + ovcap_prio = config->ovcap_prio << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG7, + BIT(config->slice_id), ovcap_prio); + if (ret) + return ret; + + vict_prio = config->vict_prio << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_ALGO_CFG8, + BIT(config->slice_id), vict_prio); + if (ret) + return ret; + } + if (config->activate_on_init) { desc.slice_id = config->slice_id; ret = llcc_slice_activate(&desc); @@ -849,7 +1000,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (ret) goto err; - drv_data->ecc_irq = platform_get_irq(pdev, 0); + drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); if (drv_data->ecc_irq >= 0) { llcc_edac = platform_device_register_data(&pdev->dev, "qcom_llcc_edac", -1, drv_data, @@ -875,6 +1026,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, + { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg }, { } }; MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); diff --git a/drivers/soc/qcom/pdr_internal.h b/drivers/soc/qcom/pdr_internal.h index a30422214943..03c282b7f17e 100644 --- a/drivers/soc/qcom/pdr_internal.h +++ b/drivers/soc/qcom/pdr_internal.h @@ -28,7 +28,7 @@ struct servreg_location_entry { u32 instance; }; -static struct qmi_elem_info servreg_location_entry_ei[] = { +static const struct qmi_elem_info servreg_location_entry_ei[] = { { .data_type = QMI_STRING, .elem_len = SERVREG_NAME_LENGTH + 1, @@ -74,7 +74,7 @@ struct servreg_get_domain_list_req { u32 domain_offset; }; -static struct qmi_elem_info servreg_get_domain_list_req_ei[] = { +static const struct qmi_elem_info servreg_get_domain_list_req_ei[] = { { .data_type = QMI_STRING, .elem_len = SERVREG_NAME_LENGTH + 1, @@ -116,7 +116,7 @@ struct servreg_get_domain_list_resp { struct servreg_location_entry domain_list[SERVREG_DOMAIN_LIST_LENGTH]; }; -static struct qmi_elem_info servreg_get_domain_list_resp_ei[] = { +static const struct qmi_elem_info servreg_get_domain_list_resp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, @@ -199,7 +199,7 @@ struct servreg_register_listener_req { char service_path[SERVREG_NAME_LENGTH + 1]; }; -static struct qmi_elem_info servreg_register_listener_req_ei[] = { +static const struct qmi_elem_info servreg_register_listener_req_ei[] = { { .data_type = QMI_UNSIGNED_1_BYTE, .elem_len = 1, @@ -227,7 +227,7 @@ struct servreg_register_listener_resp { enum servreg_service_state curr_state; }; -static struct qmi_elem_info servreg_register_listener_resp_ei[] = { +static const struct qmi_elem_info servreg_register_listener_resp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, @@ -263,7 +263,7 @@ struct servreg_restart_pd_req { char service_path[SERVREG_NAME_LENGTH + 1]; }; -static struct qmi_elem_info servreg_restart_pd_req_ei[] = { +static const struct qmi_elem_info servreg_restart_pd_req_ei[] = { { .data_type = QMI_STRING, .elem_len = SERVREG_NAME_LENGTH + 1, @@ -280,7 +280,7 @@ struct servreg_restart_pd_resp { struct qmi_response_type_v01 resp; }; -static struct qmi_elem_info servreg_restart_pd_resp_ei[] = { +static const struct qmi_elem_info servreg_restart_pd_resp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, @@ -300,7 +300,7 @@ struct servreg_state_updated_ind { u16 transaction_id; }; -static struct qmi_elem_info servreg_state_updated_ind_ei[] = { +static const struct qmi_elem_info servreg_state_updated_ind_ei[] = { { .data_type = QMI_SIGNED_4_BYTE_ENUM, .elem_len = 1, @@ -336,7 +336,7 @@ struct servreg_set_ack_req { u16 transaction_id; }; -static struct qmi_elem_info servreg_set_ack_req_ei[] = { +static const struct qmi_elem_info servreg_set_ack_req_ei[] = { { .data_type = QMI_STRING, .elem_len = SERVREG_NAME_LENGTH + 1, @@ -362,7 +362,7 @@ struct servreg_set_ack_resp { struct qmi_response_type_v01 resp; }; -static struct qmi_elem_info servreg_set_ack_resp_ei[] = { +static const struct qmi_elem_info servreg_set_ack_resp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, diff --git a/drivers/soc/qcom/qcom_stats.c b/drivers/soc/qcom/qcom_stats.c index 121ea409fafc..6228af057120 100644 --- a/drivers/soc/qcom/qcom_stats.c +++ b/drivers/soc/qcom/qcom_stats.c @@ -217,6 +217,8 @@ static int qcom_stats_probe(struct platform_device *pdev) platform_set_drvdata(pdev, root); + device_set_pm_not_required(&pdev->dev); + return 0; } diff --git a/drivers/soc/qcom/rpmh-internal.h b/drivers/soc/qcom/rpmh-internal.h index 344ba687c13b..e3cf1beff803 100644 --- a/drivers/soc/qcom/rpmh-internal.h +++ b/drivers/soc/qcom/rpmh-internal.h @@ -59,7 +59,6 @@ struct tcs_group { * @cmd: the payload that will be part of the @msg * @completion: triggered when request is done * @dev: the device making the request - * @err: err return from the controller * @needs_free: check to free dynamically allocated request object */ struct rpmh_request { @@ -67,7 +66,6 @@ struct rpmh_request { struct tcs_cmd cmd[MAX_RPMH_PAYLOAD]; struct completion *completion; const struct device *dev; - int err; bool needs_free; }; @@ -86,18 +84,25 @@ struct rpmh_ctrlr { struct list_head batch_cache; }; +struct rsc_ver { + u32 major; + u32 minor; +}; + /** * struct rsc_drv: the Direct Resource Voter (DRV) of the * Resource State Coordinator controller (RSC) * * @name: Controller identifier. + * @base: Start address of the DRV registers in this controller. * @tcs_base: Start address of the TCS registers in this controller. * @id: Instance id in the controller (Direct Resource Voter). * @num_tcs: Number of TCSes in this DRV. * @rsc_pm: CPU PM notifier for controller. * Used when solver mode is not present. * @cpus_in_pm: Number of CPUs not in idle power collapse. - * Used when solver mode is not present. + * Used when solver mode and "power-domains" is not present. + * @genpd_nb: PM Domain notifier for cluster genpd notifications. * @tcs: TCS groups. * @tcs_in_use: S/W state of the TCS; only set for ACTIVE_ONLY * transfers, but might show a sleep/wake TCS in use if @@ -110,27 +115,34 @@ struct rpmh_ctrlr { * @tcs_wait: Wait queue used to wait for @tcs_in_use to free up a * slot * @client: Handle to the DRV's client. + * @dev: RSC device. */ struct rsc_drv { const char *name; + void __iomem *base; void __iomem *tcs_base; int id; int num_tcs; struct notifier_block rsc_pm; + struct notifier_block genpd_nb; atomic_t cpus_in_pm; struct tcs_group tcs[TCS_TYPE_NR]; DECLARE_BITMAP(tcs_in_use, MAX_TCS_NR); spinlock_t lock; wait_queue_head_t tcs_wait; struct rpmh_ctrlr client; + struct device *dev; + struct rsc_ver ver; + u32 *regs; }; int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg); int rpmh_rsc_write_ctrl_data(struct rsc_drv *drv, const struct tcs_request *msg); void rpmh_rsc_invalidate(struct rsc_drv *drv); +void rpmh_rsc_write_next_wakeup(struct rsc_drv *drv); -void rpmh_tx_done(const struct tcs_request *msg, int r); +void rpmh_tx_done(const struct tcs_request *msg); int rpmh_flush(struct rpmh_ctrlr *ctrlr); #endif /* __RPM_INTERNAL_H__ */ diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 01c2f50cb97e..0f8b2249f889 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -12,16 +12,21 @@ #include <linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> +#include <linux/ktime.h> #include <linux/list.h> #include <linux/module.h> +#include <linux/notifier.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/platform_device.h> +#include <linux/pm_domain.h> +#include <linux/pm_runtime.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/wait.h> +#include <clocksource/arm_arch_timer.h> #include <soc/qcom/cmd-db.h> #include <soc/qcom/tcs.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -31,49 +36,50 @@ #define CREATE_TRACE_POINTS #include "trace-rpmh.h" -#define RSC_DRV_TCS_OFFSET 672 -#define RSC_DRV_CMD_OFFSET 20 + +#define RSC_DRV_ID 0 + +#define MAJOR_VER_MASK 0xFF +#define MAJOR_VER_SHIFT 16 +#define MINOR_VER_MASK 0xFF +#define MINOR_VER_SHIFT 8 + +enum { + RSC_DRV_TCS_OFFSET, + RSC_DRV_CMD_OFFSET, + DRV_SOLVER_CONFIG, + DRV_PRNT_CHLD_CONFIG, + RSC_DRV_IRQ_ENABLE, + RSC_DRV_IRQ_STATUS, + RSC_DRV_IRQ_CLEAR, + RSC_DRV_CMD_WAIT_FOR_CMPL, + RSC_DRV_CONTROL, + RSC_DRV_STATUS, + RSC_DRV_CMD_ENABLE, + RSC_DRV_CMD_MSGID, + RSC_DRV_CMD_ADDR, + RSC_DRV_CMD_DATA, + RSC_DRV_CMD_STATUS, + RSC_DRV_CMD_RESP_DATA, +}; /* DRV HW Solver Configuration Information Register */ -#define DRV_SOLVER_CONFIG 0x04 #define DRV_HW_SOLVER_MASK 1 #define DRV_HW_SOLVER_SHIFT 24 /* DRV TCS Configuration Information Register */ -#define DRV_PRNT_CHLD_CONFIG 0x0C #define DRV_NUM_TCS_MASK 0x3F #define DRV_NUM_TCS_SHIFT 6 #define DRV_NCPT_MASK 0x1F #define DRV_NCPT_SHIFT 27 -/* Offsets for common TCS Registers, one bit per TCS */ -#define RSC_DRV_IRQ_ENABLE 0x00 -#define RSC_DRV_IRQ_STATUS 0x04 -#define RSC_DRV_IRQ_CLEAR 0x08 /* w/o; write 1 to clear */ - -/* - * Offsets for per TCS Registers. - * - * TCSes start at 0x10 from tcs_base and are stored one after another. - * Multiply tcs_id by RSC_DRV_TCS_OFFSET to find a given TCS and add one - * of the below to find a register. - */ -#define RSC_DRV_CMD_WAIT_FOR_CMPL 0x10 /* 1 bit per command */ -#define RSC_DRV_CONTROL 0x14 -#define RSC_DRV_STATUS 0x18 /* zero if tcs is busy */ -#define RSC_DRV_CMD_ENABLE 0x1C /* 1 bit per command */ - -/* - * Offsets for per command in a TCS. - * - * Commands (up to 16) start at 0x30 in a TCS; multiply command index - * by RSC_DRV_CMD_OFFSET and add one of the below to find a register. - */ -#define RSC_DRV_CMD_MSGID 0x30 -#define RSC_DRV_CMD_ADDR 0x34 -#define RSC_DRV_CMD_DATA 0x38 -#define RSC_DRV_CMD_STATUS 0x3C -#define RSC_DRV_CMD_RESP_DATA 0x40 +/* Offsets for CONTROL TCS Registers */ +#define RSC_DRV_CTL_TCS_DATA_HI 0x38 +#define RSC_DRV_CTL_TCS_DATA_HI_MASK 0xFFFFFF +#define RSC_DRV_CTL_TCS_DATA_HI_VALID BIT(31) +#define RSC_DRV_CTL_TCS_DATA_LO 0x40 +#define RSC_DRV_CTL_TCS_DATA_LO_MASK 0xFFFFFFFF +#define RSC_DRV_CTL_TCS_DATA_SIZE 32 #define TCS_AMC_MODE_ENABLE BIT(16) #define TCS_AMC_MODE_TRIGGER BIT(24) @@ -139,16 +145,62 @@ * +---------------------------------------------------+ */ +#define USECS_TO_CYCLES(time_usecs) \ + xloops_to_cycles((time_usecs) * 0x10C7UL) + +static inline unsigned long xloops_to_cycles(u64 xloops) +{ + return (xloops * loops_per_jiffy * HZ) >> 32; +} + +static u32 rpmh_rsc_reg_offset_ver_2_7[] = { + [RSC_DRV_TCS_OFFSET] = 672, + [RSC_DRV_CMD_OFFSET] = 20, + [DRV_SOLVER_CONFIG] = 0x04, + [DRV_PRNT_CHLD_CONFIG] = 0x0C, + [RSC_DRV_IRQ_ENABLE] = 0x00, + [RSC_DRV_IRQ_STATUS] = 0x04, + [RSC_DRV_IRQ_CLEAR] = 0x08, + [RSC_DRV_CMD_WAIT_FOR_CMPL] = 0x10, + [RSC_DRV_CONTROL] = 0x14, + [RSC_DRV_STATUS] = 0x18, + [RSC_DRV_CMD_ENABLE] = 0x1C, + [RSC_DRV_CMD_MSGID] = 0x30, + [RSC_DRV_CMD_ADDR] = 0x34, + [RSC_DRV_CMD_DATA] = 0x38, + [RSC_DRV_CMD_STATUS] = 0x3C, + [RSC_DRV_CMD_RESP_DATA] = 0x40, +}; + +static u32 rpmh_rsc_reg_offset_ver_3_0[] = { + [RSC_DRV_TCS_OFFSET] = 672, + [RSC_DRV_CMD_OFFSET] = 24, + [DRV_SOLVER_CONFIG] = 0x04, + [DRV_PRNT_CHLD_CONFIG] = 0x0C, + [RSC_DRV_IRQ_ENABLE] = 0x00, + [RSC_DRV_IRQ_STATUS] = 0x04, + [RSC_DRV_IRQ_CLEAR] = 0x08, + [RSC_DRV_CMD_WAIT_FOR_CMPL] = 0x20, + [RSC_DRV_CONTROL] = 0x24, + [RSC_DRV_STATUS] = 0x28, + [RSC_DRV_CMD_ENABLE] = 0x2C, + [RSC_DRV_CMD_MSGID] = 0x34, + [RSC_DRV_CMD_ADDR] = 0x38, + [RSC_DRV_CMD_DATA] = 0x3C, + [RSC_DRV_CMD_STATUS] = 0x40, + [RSC_DRV_CMD_RESP_DATA] = 0x44, +}; + static inline void __iomem * tcs_reg_addr(const struct rsc_drv *drv, int reg, int tcs_id) { - return drv->tcs_base + RSC_DRV_TCS_OFFSET * tcs_id + reg; + return drv->tcs_base + drv->regs[RSC_DRV_TCS_OFFSET] * tcs_id + reg; } static inline void __iomem * tcs_cmd_addr(const struct rsc_drv *drv, int reg, int tcs_id, int cmd_id) { - return tcs_reg_addr(drv, reg, tcs_id) + RSC_DRV_CMD_OFFSET * cmd_id; + return tcs_reg_addr(drv, reg, tcs_id) + drv->regs[RSC_DRV_CMD_OFFSET] * cmd_id; } static u32 read_tcs_cmd(const struct rsc_drv *drv, int reg, int tcs_id, @@ -216,7 +268,7 @@ static void tcs_invalidate(struct rsc_drv *drv, int type) return; for (m = tcs->offset; m < tcs->offset + tcs->num_tcs; m++) - write_tcs_reg_sync(drv, RSC_DRV_CMD_ENABLE, m, 0); + write_tcs_reg_sync(drv, drv->regs[RSC_DRV_CMD_ENABLE], m, 0); bitmap_zero(tcs->slots, MAX_TCS_SLOTS); } @@ -330,24 +382,25 @@ static const struct tcs_request *get_req_from_tcs(struct rsc_drv *drv, static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger) { u32 enable; + u32 reg = drv->regs[RSC_DRV_CONTROL]; /* * HW req: Clear the DRV_CONTROL and enable TCS again * While clearing ensure that the AMC mode trigger is cleared * and then the mode enable is cleared. */ - enable = read_tcs_reg(drv, RSC_DRV_CONTROL, tcs_id); + enable = read_tcs_reg(drv, reg, tcs_id); enable &= ~TCS_AMC_MODE_TRIGGER; - write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); + write_tcs_reg_sync(drv, reg, tcs_id, enable); enable &= ~TCS_AMC_MODE_ENABLE; - write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); + write_tcs_reg_sync(drv, reg, tcs_id, enable); if (trigger) { /* Enable the AMC mode on the TCS and then trigger the TCS */ enable = TCS_AMC_MODE_ENABLE; - write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable); + write_tcs_reg_sync(drv, reg, tcs_id, enable); enable |= TCS_AMC_MODE_TRIGGER; - write_tcs_reg(drv, RSC_DRV_CONTROL, tcs_id, enable); + write_tcs_reg(drv, reg, tcs_id, enable); } } @@ -363,13 +416,14 @@ static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger) static void enable_tcs_irq(struct rsc_drv *drv, int tcs_id, bool enable) { u32 data; + u32 reg = drv->regs[RSC_DRV_IRQ_ENABLE]; - data = readl_relaxed(drv->tcs_base + RSC_DRV_IRQ_ENABLE); + data = readl_relaxed(drv->tcs_base + reg); if (enable) data |= BIT(tcs_id); else data &= ~BIT(tcs_id); - writel_relaxed(data, drv->tcs_base + RSC_DRV_IRQ_ENABLE); + writel_relaxed(data, drv->tcs_base + reg); } /** @@ -385,34 +439,18 @@ static void enable_tcs_irq(struct rsc_drv *drv, int tcs_id, bool enable) static irqreturn_t tcs_tx_done(int irq, void *p) { struct rsc_drv *drv = p; - int i, j, err = 0; + int i; unsigned long irq_status; const struct tcs_request *req; - struct tcs_cmd *cmd; - irq_status = readl_relaxed(drv->tcs_base + RSC_DRV_IRQ_STATUS); + irq_status = readl_relaxed(drv->tcs_base + drv->regs[RSC_DRV_IRQ_STATUS]); for_each_set_bit(i, &irq_status, BITS_PER_TYPE(u32)) { req = get_req_from_tcs(drv, i); if (WARN_ON(!req)) goto skip; - err = 0; - for (j = 0; j < req->num_cmds; j++) { - u32 sts; - - cmd = &req->cmds[j]; - sts = read_tcs_cmd(drv, RSC_DRV_CMD_STATUS, i, j); - if (!(sts & CMD_STATUS_ISSUED) || - ((req->wait_for_compl || cmd->wait) && - !(sts & CMD_STATUS_COMPL))) { - pr_err("Incomplete request: %s: addr=%#x data=%#x", - drv->name, cmd->addr, cmd->data); - err = -EIO; - } - } - - trace_rpmh_tx_done(drv, i, req, err); + trace_rpmh_tx_done(drv, i, req); /* * If wake tcs was re-purposed for sending active @@ -423,8 +461,8 @@ static irqreturn_t tcs_tx_done(int irq, void *p) __tcs_set_trigger(drv, i, false); skip: /* Reclaim the TCS */ - write_tcs_reg(drv, RSC_DRV_CMD_ENABLE, i, 0); - writel_relaxed(BIT(i), drv->tcs_base + RSC_DRV_IRQ_CLEAR); + write_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], i, 0); + writel_relaxed(BIT(i), drv->tcs_base + drv->regs[RSC_DRV_IRQ_CLEAR]); spin_lock(&drv->lock); clear_bit(i, drv->tcs_in_use); /* @@ -437,7 +475,7 @@ skip: spin_unlock(&drv->lock); wake_up(&drv->tcs_wait); if (req) - rpmh_tx_done(req, err); + rpmh_tx_done(req); } return IRQ_HANDLED; @@ -475,14 +513,14 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id, */ msgid |= cmd->wait ? CMD_MSGID_RESP_REQ : 0; - write_tcs_cmd(drv, RSC_DRV_CMD_MSGID, tcs_id, j, msgid); - write_tcs_cmd(drv, RSC_DRV_CMD_ADDR, tcs_id, j, cmd->addr); - write_tcs_cmd(drv, RSC_DRV_CMD_DATA, tcs_id, j, cmd->data); + write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_MSGID], tcs_id, j, msgid); + write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], tcs_id, j, cmd->addr); + write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_DATA], tcs_id, j, cmd->data); trace_rpmh_send_msg(drv, tcs_id, j, msgid, cmd); } - cmd_enable |= read_tcs_reg(drv, RSC_DRV_CMD_ENABLE, tcs_id); - write_tcs_reg(drv, RSC_DRV_CMD_ENABLE, tcs_id, cmd_enable); + cmd_enable |= read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id); + write_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id, cmd_enable); } /** @@ -514,10 +552,10 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs, int i = tcs->offset; for_each_set_bit_from(i, drv->tcs_in_use, tcs->offset + tcs->num_tcs) { - curr_enabled = read_tcs_reg(drv, RSC_DRV_CMD_ENABLE, i); + curr_enabled = read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], i); for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) { - addr = read_tcs_cmd(drv, RSC_DRV_CMD_ADDR, i, j); + addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j); for (k = 0; k < msg->num_cmds; k++) { if (addr == msg->cmds[k].addr) return -EBUSY; @@ -628,7 +666,7 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg) * repurposed TCS to avoid triggering them. tcs->slots will be * cleaned from rpmh_flush() by invoking rpmh_rsc_invalidate() */ - write_tcs_reg_sync(drv, RSC_DRV_CMD_ENABLE, tcs_id, 0); + write_tcs_reg_sync(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id, 0); enable_tcs_irq(drv, tcs_id, true); } spin_unlock_irqrestore(&drv->lock, flags); @@ -754,6 +792,48 @@ static bool rpmh_rsc_ctrlr_is_busy(struct rsc_drv *drv) } /** + * rpmh_rsc_write_next_wakeup() - Write next wakeup in CONTROL_TCS. + * @drv: The controller + * + * Writes maximum wakeup cycles when called from suspend. + * Writes earliest hrtimer wakeup when called from idle. + */ +void rpmh_rsc_write_next_wakeup(struct rsc_drv *drv) +{ + ktime_t now, wakeup; + u64 wakeup_us, wakeup_cycles = ~0; + u32 lo, hi; + + if (!drv->tcs[CONTROL_TCS].num_tcs || !drv->genpd_nb.notifier_call) + return; + + /* Set highest time when system (timekeeping) is suspended */ + if (system_state == SYSTEM_SUSPEND) + goto exit; + + /* Find the earliest hrtimer wakeup from online cpus */ + wakeup = dev_pm_genpd_get_next_hrtimer(drv->dev); + + /* Find the relative wakeup in kernel time scale */ + now = ktime_get(); + wakeup = ktime_sub(wakeup, now); + wakeup_us = ktime_to_us(wakeup); + + /* Convert the wakeup to arch timer scale */ + wakeup_cycles = USECS_TO_CYCLES(wakeup_us); + wakeup_cycles += arch_timer_read_counter(); + +exit: + lo = wakeup_cycles & RSC_DRV_CTL_TCS_DATA_LO_MASK; + hi = wakeup_cycles >> RSC_DRV_CTL_TCS_DATA_SIZE; + hi &= RSC_DRV_CTL_TCS_DATA_HI_MASK; + hi |= RSC_DRV_CTL_TCS_DATA_HI_VALID; + + writel_relaxed(lo, drv->base + RSC_DRV_CTL_TCS_DATA_LO); + writel_relaxed(hi, drv->base + RSC_DRV_CTL_TCS_DATA_HI); +} + +/** * rpmh_rsc_cpu_pm_callback() - Check if any of the AMCs are busy. * @nfb: Pointer to the notifier block in struct rsc_drv. * @action: CPU_PM_ENTER, CPU_PM_ENTER_FAILED, or CPU_PM_EXIT. @@ -834,8 +914,51 @@ static int rpmh_rsc_cpu_pm_callback(struct notifier_block *nfb, return ret; } -static int rpmh_probe_tcs_config(struct platform_device *pdev, - struct rsc_drv *drv, void __iomem *base) +/** + * rpmh_rsc_pd_callback() - Check if any of the AMCs are busy. + * @nfb: Pointer to the genpd notifier block in struct rsc_drv. + * @action: GENPD_NOTIFY_PRE_OFF, GENPD_NOTIFY_OFF, GENPD_NOTIFY_PRE_ON or GENPD_NOTIFY_ON. + * @v: Unused + * + * This function is given to dev_pm_genpd_add_notifier() so we can be informed + * about when cluster-pd is going down. When cluster go down we know no more active + * transfers will be started so we write sleep/wake sets. This function gets + * called from cpuidle code paths and also at system suspend time. + * + * If AMCs are not busy then writes cached sleep and wake messages to TCSes. + * The firmware then takes care of triggering them when entering deepest low power modes. + * + * Return: + * * NOTIFY_OK - success + * * NOTIFY_BAD - failure + */ +static int rpmh_rsc_pd_callback(struct notifier_block *nfb, + unsigned long action, void *v) +{ + struct rsc_drv *drv = container_of(nfb, struct rsc_drv, genpd_nb); + + /* We don't need to lock as genpd on/off are serialized */ + if ((action == GENPD_NOTIFY_PRE_OFF) && + (rpmh_rsc_ctrlr_is_busy(drv) || rpmh_flush(&drv->client))) + return NOTIFY_BAD; + + return NOTIFY_OK; +} + +static int rpmh_rsc_pd_attach(struct rsc_drv *drv, struct device *dev) +{ + int ret; + + pm_runtime_enable(dev); + drv->genpd_nb.notifier_call = rpmh_rsc_pd_callback; + ret = dev_pm_genpd_add_notifier(dev, &drv->genpd_nb); + if (ret) + pm_runtime_disable(dev); + + return ret; +} + +static int rpmh_probe_tcs_config(struct platform_device *pdev, struct rsc_drv *drv) { struct tcs_type_config { u32 type; @@ -849,9 +972,9 @@ static int rpmh_probe_tcs_config(struct platform_device *pdev, ret = of_property_read_u32(dn, "qcom,tcs-offset", &offset); if (ret) return ret; - drv->tcs_base = base + offset; + drv->tcs_base = drv->base + offset; - config = readl_relaxed(base + DRV_PRNT_CHLD_CONFIG); + config = readl_relaxed(drv->base + drv->regs[DRV_PRNT_CHLD_CONFIG]); max_tcs = config; max_tcs &= DRV_NUM_TCS_MASK << (DRV_NUM_TCS_SHIFT * drv->id); @@ -913,7 +1036,7 @@ static int rpmh_rsc_probe(struct platform_device *pdev) char drv_id[10] = {0}; int ret, irq; u32 solver_config; - void __iomem *base; + u32 rsc_id; /* * Even though RPMh doesn't directly use cmd-db, all of its children @@ -940,11 +1063,22 @@ static int rpmh_rsc_probe(struct platform_device *pdev) drv->name = dev_name(&pdev->dev); snprintf(drv_id, ARRAY_SIZE(drv_id), "drv-%d", drv->id); - base = devm_platform_ioremap_resource_byname(pdev, drv_id); - if (IS_ERR(base)) - return PTR_ERR(base); + drv->base = devm_platform_ioremap_resource_byname(pdev, drv_id); + if (IS_ERR(drv->base)) + return PTR_ERR(drv->base); + + rsc_id = readl_relaxed(drv->base + RSC_DRV_ID); + drv->ver.major = rsc_id & (MAJOR_VER_MASK << MAJOR_VER_SHIFT); + drv->ver.major >>= MAJOR_VER_SHIFT; + drv->ver.minor = rsc_id & (MINOR_VER_MASK << MINOR_VER_SHIFT); + drv->ver.minor >>= MINOR_VER_SHIFT; + + if (drv->ver.major == 3 && drv->ver.minor == 0) + drv->regs = rpmh_rsc_reg_offset_ver_3_0; + else + drv->regs = rpmh_rsc_reg_offset_ver_2_7; - ret = rpmh_probe_tcs_config(pdev, drv, base); + ret = rpmh_probe_tcs_config(pdev, drv); if (ret) return ret; @@ -963,29 +1097,42 @@ static int rpmh_rsc_probe(struct platform_device *pdev) return ret; /* - * CPU PM notification are not required for controllers that support + * CPU PM/genpd notification are not required for controllers that support * 'HW solver' mode where they can be in autonomous mode executing low * power mode to power down. */ - solver_config = readl_relaxed(base + DRV_SOLVER_CONFIG); + solver_config = readl_relaxed(drv->base + drv->regs[DRV_SOLVER_CONFIG]); solver_config &= DRV_HW_SOLVER_MASK << DRV_HW_SOLVER_SHIFT; solver_config = solver_config >> DRV_HW_SOLVER_SHIFT; if (!solver_config) { - drv->rsc_pm.notifier_call = rpmh_rsc_cpu_pm_callback; - cpu_pm_register_notifier(&drv->rsc_pm); + if (pdev->dev.pm_domain) { + ret = rpmh_rsc_pd_attach(drv, &pdev->dev); + if (ret) + return ret; + } else { + drv->rsc_pm.notifier_call = rpmh_rsc_cpu_pm_callback; + cpu_pm_register_notifier(&drv->rsc_pm); + } } /* Enable the active TCS to send requests immediately */ writel_relaxed(drv->tcs[ACTIVE_TCS].mask, - drv->tcs_base + RSC_DRV_IRQ_ENABLE); + drv->tcs_base + drv->regs[RSC_DRV_IRQ_ENABLE]); spin_lock_init(&drv->client.cache_lock); INIT_LIST_HEAD(&drv->client.cache); INIT_LIST_HEAD(&drv->client.batch_cache); dev_set_drvdata(&pdev->dev, drv); + drv->dev = &pdev->dev; + + ret = devm_of_platform_populate(&pdev->dev); + if (ret && pdev->dev.pm_domain) { + dev_pm_genpd_remove_notifier(&pdev->dev); + pm_runtime_disable(&pdev->dev); + } - return devm_of_platform_populate(&pdev->dev); + return ret; } static const struct of_device_id rpmh_drv_match[] = { diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c index 01765ee9cdfb..08e09642d7f5 100644 --- a/drivers/soc/qcom/rpmh.c +++ b/drivers/soc/qcom/rpmh.c @@ -76,19 +76,13 @@ static struct rpmh_ctrlr *get_rpmh_ctrlr(const struct device *dev) return &drv->client; } -void rpmh_tx_done(const struct tcs_request *msg, int r) +void rpmh_tx_done(const struct tcs_request *msg) { struct rpmh_request *rpm_msg = container_of(msg, struct rpmh_request, msg); struct completion *compl = rpm_msg->completion; bool free = rpm_msg->needs_free; - rpm_msg->err = r; - - if (r) - dev_err(rpm_msg->dev, "RPMH TX fail in msg addr=%#x, err=%d\n", - rpm_msg->msg.cmds[0].addr, r); - if (!compl) goto exit; @@ -194,7 +188,7 @@ static int __rpmh_write(const struct device *dev, enum rpmh_state state, } else { /* Clean up our call by spoofing tx_done */ ret = 0; - rpmh_tx_done(&rpm_msg->msg, ret); + rpmh_tx_done(&rpm_msg->msg); } return ret; @@ -450,7 +444,7 @@ int rpmh_flush(struct rpmh_ctrlr *ctrlr) if (!ctrlr->dirty) { pr_debug("Skipping flush, TCS has latest data.\n"); - goto exit; + goto write_next_wakeup; } /* Invalidate the TCSes first to avoid stale data */ @@ -479,6 +473,8 @@ int rpmh_flush(struct rpmh_ctrlr *ctrlr) ctrlr->dirty = false; +write_next_wakeup: + rpmh_rsc_write_next_wakeup(ctrlr_to_drv(ctrlr)); exit: spin_unlock(&ctrlr->cache_lock); return ret; diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 092f6ab09acf..4c2d2c296790 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -39,6 +39,7 @@ * @res_name: Resource name used for cmd-db lookup * @addr: Resource address as looped up using resource name from * cmd-db + * @state_synced: Indicator that sync_state has been invoked for the rpmhpd resource */ struct rpmhpd { struct device *dev; @@ -54,6 +55,7 @@ struct rpmhpd { bool enabled; const char *res_name; u32 addr; + bool state_synced; }; struct rpmhpd_desc { @@ -210,6 +212,23 @@ static const struct rpmhpd_desc sa8540p_desc = { .num_pds = ARRAY_SIZE(sa8540p_rpmhpds), }; +/* SDM670 RPMH powerdomains */ +static struct rpmhpd *sdm670_rpmhpds[] = { + [SDM670_CX] = &cx_w_mx_parent, + [SDM670_CX_AO] = &cx_ao_w_mx_parent, + [SDM670_GFX] = &gfx, + [SDM670_LCX] = &lcx, + [SDM670_LMX] = &lmx, + [SDM670_MSS] = &mss, + [SDM670_MX] = &mx, + [SDM670_MX_AO] = &mx_ao, +}; + +static const struct rpmhpd_desc sdm670_desc = { + .rpmhpds = sdm670_rpmhpds, + .num_pds = ARRAY_SIZE(sdm670_rpmhpds), +}; + /* SDM845 RPMH powerdomains */ static struct rpmhpd *sdm845_rpmhpds[] = { [SDM845_CX] = &cx_w_mx_parent, @@ -353,6 +372,42 @@ static const struct rpmhpd_desc sm8450_desc = { .num_pds = ARRAY_SIZE(sm8450_rpmhpds), }; +/* SM8550 RPMH powerdomains */ +static struct rpmhpd *sm8550_rpmhpds[] = { + [SM8550_CX] = &cx, + [SM8550_CX_AO] = &cx_ao, + [SM8550_EBI] = &ebi, + [SM8550_GFX] = &gfx, + [SM8550_LCX] = &lcx, + [SM8550_LMX] = &lmx, + [SM8550_MMCX] = &mmcx_w_cx_parent, + [SM8550_MMCX_AO] = &mmcx_ao_w_cx_parent, + [SM8550_MSS] = &mss, + [SM8550_MX] = &mx, + [SM8550_MX_AO] = &mx_ao, + [SM8550_MXC] = &mxc, + [SM8550_MXC_AO] = &mxc_ao, + [SM8550_NSP] = &nsp, +}; + +static const struct rpmhpd_desc sm8550_desc = { + .rpmhpds = sm8550_rpmhpds, + .num_pds = ARRAY_SIZE(sm8550_rpmhpds), +}; + +/* QDU1000/QRU1000 RPMH powerdomains */ +static struct rpmhpd *qdu1000_rpmhpds[] = { + [QDU1000_CX] = &cx, + [QDU1000_EBI] = &ebi, + [QDU1000_MSS] = &mss, + [QDU1000_MX] = &mx, +}; + +static const struct rpmhpd_desc qdu1000_desc = { + .rpmhpds = qdu1000_rpmhpds, + .num_pds = ARRAY_SIZE(qdu1000_rpmhpds), +}; + /* SC7180 RPMH powerdomains */ static struct rpmhpd *sc7180_rpmhpds[] = { [SC7180_CX] = &cx_w_mx_parent, @@ -430,11 +485,13 @@ static const struct rpmhpd_desc sc8280xp_desc = { }; static const struct of_device_id rpmhpd_match_table[] = { + { .compatible = "qcom,qdu1000-rpmhpd", .data = &qdu1000_desc }, { .compatible = "qcom,sa8540p-rpmhpd", .data = &sa8540p_desc }, { .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc }, { .compatible = "qcom,sc7280-rpmhpd", .data = &sc7280_desc }, { .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc }, { .compatible = "qcom,sc8280xp-rpmhpd", .data = &sc8280xp_desc }, + { .compatible = "qcom,sdm670-rpmhpd", .data = &sdm670_desc }, { .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc }, { .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc}, { .compatible = "qcom,sdx65-rpmhpd", .data = &sdx65_desc}, @@ -443,6 +500,7 @@ static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc }, { .compatible = "qcom,sm8350-rpmhpd", .data = &sm8350_desc }, { .compatible = "qcom,sm8450-rpmhpd", .data = &sm8450_desc }, + { .compatible = "qcom,sm8550-rpmhpd", .data = &sm8550_desc }, { } }; MODULE_DEVICE_TABLE(of, rpmhpd_match_table); @@ -493,7 +551,13 @@ static int rpmhpd_aggregate_corner(struct rpmhpd *pd, unsigned int corner) unsigned int this_active_corner = 0, this_sleep_corner = 0; unsigned int peer_active_corner = 0, peer_sleep_corner = 0; - to_active_sleep(pd, corner, &this_active_corner, &this_sleep_corner); + if (pd->state_synced) { + to_active_sleep(pd, corner, &this_active_corner, &this_sleep_corner); + } else { + /* Clamp to highest corner if sync_state hasn't happened */ + this_active_corner = pd->level_count - 1; + this_sleep_corner = pd->level_count - 1; + } if (peer && peer->enabled) to_active_sleep(peer, peer->corner, &peer_active_corner, @@ -708,11 +772,40 @@ static int rpmhpd_probe(struct platform_device *pdev) return of_genpd_add_provider_onecell(pdev->dev.of_node, data); } +static void rpmhpd_sync_state(struct device *dev) +{ + const struct rpmhpd_desc *desc = of_device_get_match_data(dev); + struct rpmhpd **rpmhpds = desc->rpmhpds; + unsigned int corner; + struct rpmhpd *pd; + unsigned int i; + int ret; + + mutex_lock(&rpmhpd_lock); + for (i = 0; i < desc->num_pds; i++) { + pd = rpmhpds[i]; + if (!pd) + continue; + + pd->state_synced = true; + if (pd->enabled) + corner = max(pd->corner, pd->enable_corner); + else + corner = 0; + + ret = rpmhpd_aggregate_corner(pd, corner); + if (ret) + dev_err(dev, "failed to sync %s\n", pd->res_name); + } + mutex_unlock(&rpmhpd_lock); +} + static struct platform_driver rpmhpd_driver = { .driver = { .name = "qcom-rpmhpd", .of_match_table = rpmhpd_match_table, .suppress_bind_attrs = true, + .sync_state = rpmhpd_sync_state, }, .probe = rpmhpd_probe, }; diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 337b1ad1cd3b..f0db6a10cf4e 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -471,6 +471,23 @@ static const struct rpmpd_desc qcm2290_desc = { .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, }; +static struct rpmpd *sm4250_rpmpds[] = { + [SM4250_VDDCX] = &sm6115_vddcx, + [SM4250_VDDCX_AO] = &sm6115_vddcx_ao, + [SM4250_VDDCX_VFL] = &sm6115_vddcx_vfl, + [SM4250_VDDMX] = &sm6115_vddmx, + [SM4250_VDDMX_AO] = &sm6115_vddmx_ao, + [SM4250_VDDMX_VFL] = &sm6115_vddmx_vfl, + [SM4250_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, + [SM4250_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, +}; + +static const struct rpmpd_desc sm4250_desc = { + .rpmpds = sm4250_rpmpds, + .num_pds = ARRAY_SIZE(sm4250_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, +}; + static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, { .compatible = "qcom,msm8226-rpmpd", .data = &msm8226_desc }, @@ -485,6 +502,7 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,qcm2290-rpmpd", .data = &qcm2290_desc }, { .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc }, { .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc }, + { .compatible = "qcom,sm4250-rpmpd", .data = &sm4250_desc }, { .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc }, { .compatible = "qcom,sm6125-rpmpd", .data = &sm6125_desc }, { .compatible = "qcom,sm6375-rpmpd", .data = &sm6375_desc }, diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index 413f9f4ae9cd..7e3b6a7ea34c 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -75,7 +75,7 @@ struct qcom_rpm_message { __le32 length; union { __le32 msg_id; - u8 message[0]; + DECLARE_FLEX_ARRAY(u8, message); }; }; @@ -246,6 +246,7 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = { { .compatible = "qcom,rpm-sdm660" }, { .compatible = "qcom,rpm-sm6115" }, { .compatible = "qcom,rpm-sm6125" }, + { .compatible = "qcom,rpm-sm6375" }, { .compatible = "qcom,rpm-qcm2290" }, { .compatible = "qcom,rpm-qcs404" }, {} diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index d9c28a8a7cbf..e9c8030d50ee 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -422,7 +422,7 @@ static int qcom_smp2p_outbound_entry(struct qcom_smp2p *smp2p, char buf[SMP2P_MAX_ENTRY_NAME] = {}; /* Allocate an entry from the smem item */ - strlcpy(buf, entry->name, SMP2P_MAX_ENTRY_NAME); + strscpy(buf, entry->name, SMP2P_MAX_ENTRY_NAME); memcpy(out->entries[out->valid_entries].name, buf, SMP2P_MAX_ENTRY_NAME); /* Make the logical entry reference the physical value */ diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index aa37e1bad095..ebcbf9b9c18b 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -12,11 +12,14 @@ #include <linux/slab.h> #include <linux/soc/qcom/smem.h> #include <linux/string.h> +#include <linux/stringify.h> #include <linux/sys_soc.h> #include <linux/types.h> #include <asm/unaligned.h> +#include <dt-bindings/arm/qcom,ids.h> + /* * SoC version type with major number in the upper 16 bits and minor * number in the lower 16 bits. @@ -25,6 +28,10 @@ #define SOCINFO_MINOR(ver) ((ver) & 0xffff) #define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) +/* Helper macros to create soc_id table */ +#define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id) +#define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name) + #define SMEM_SOCINFO_BUILD_ID_LENGTH 32 #define SMEM_SOCINFO_CHIP_ID_LENGTH 32 @@ -207,135 +214,150 @@ struct soc_id { }; static const struct soc_id soc_id[] = { - { 87, "MSM8960" }, - { 109, "APQ8064" }, - { 122, "MSM8660A" }, - { 123, "MSM8260A" }, - { 124, "APQ8060A" }, - { 126, "MSM8974" }, - { 130, "MPQ8064" }, - { 138, "MSM8960AB" }, - { 139, "APQ8060AB" }, - { 140, "MSM8260AB" }, - { 141, "MSM8660AB" }, - { 145, "MSM8626" }, - { 147, "MSM8610" }, - { 153, "APQ8064AB" }, - { 158, "MSM8226" }, - { 159, "MSM8526" }, - { 161, "MSM8110" }, - { 162, "MSM8210" }, - { 163, "MSM8810" }, - { 164, "MSM8212" }, - { 165, "MSM8612" }, - { 166, "MSM8112" }, - { 168, "MSM8225Q" }, - { 169, "MSM8625Q" }, - { 170, "MSM8125Q" }, - { 172, "APQ8064AA" }, - { 178, "APQ8084" }, - { 184, "APQ8074" }, - { 185, "MSM8274" }, - { 186, "MSM8674" }, - { 194, "MSM8974PRO-AC" }, - { 198, "MSM8126" }, - { 199, "APQ8026" }, - { 200, "MSM8926" }, - { 205, "MSM8326" }, - { 206, "MSM8916" }, - { 207, "MSM8994" }, - { 208, "APQ8074PRO-AA" }, - { 209, "APQ8074PRO-AB" }, - { 210, "APQ8074PRO-AC" }, - { 211, "MSM8274PRO-AA" }, - { 212, "MSM8274PRO-AB" }, - { 213, "MSM8274PRO-AC" }, - { 214, "MSM8674PRO-AA" }, - { 215, "MSM8674PRO-AB" }, - { 216, "MSM8674PRO-AC" }, - { 217, "MSM8974PRO-AA" }, - { 218, "MSM8974PRO-AB" }, - { 219, "APQ8028" }, - { 220, "MSM8128" }, - { 221, "MSM8228" }, - { 222, "MSM8528" }, - { 223, "MSM8628" }, - { 224, "MSM8928" }, - { 225, "MSM8510" }, - { 226, "MSM8512" }, - { 233, "MSM8936" }, - { 239, "MSM8939" }, - { 240, "APQ8036" }, - { 241, "APQ8039" }, - { 246, "MSM8996" }, - { 247, "APQ8016" }, - { 248, "MSM8216" }, - { 249, "MSM8116" }, - { 250, "MSM8616" }, - { 251, "MSM8992" }, - { 253, "APQ8094" }, - { 290, "MDM9607" }, - { 291, "APQ8096" }, - { 292, "MSM8998" }, - { 293, "MSM8953" }, - { 296, "MDM8207" }, - { 297, "MDM9207" }, - { 298, "MDM9307" }, - { 299, "MDM9628" }, - { 304, "APQ8053" }, - { 305, "MSM8996SG" }, - { 310, "MSM8996AU" }, - { 311, "APQ8096AU" }, - { 312, "APQ8096SG" }, - { 317, "SDM660" }, - { 318, "SDM630" }, - { 319, "APQ8098" }, - { 321, "SDM845" }, - { 322, "MDM9206" }, - { 323, "IPQ8074" }, - { 324, "SDA660" }, - { 325, "SDM658" }, - { 326, "SDA658" }, - { 327, "SDA630" }, - { 338, "SDM450" }, - { 341, "SDA845" }, - { 342, "IPQ8072" }, - { 343, "IPQ8076" }, - { 344, "IPQ8078" }, - { 345, "SDM636" }, - { 346, "SDA636" }, - { 349, "SDM632" }, - { 350, "SDA632" }, - { 351, "SDA450" }, - { 356, "SM8250" }, - { 375, "IPQ8070" }, - { 376, "IPQ8071" }, - { 389, "IPQ8072A" }, - { 390, "IPQ8074A" }, - { 391, "IPQ8076A" }, - { 392, "IPQ8078A" }, - { 394, "SM6125" }, - { 395, "IPQ8070A" }, - { 396, "IPQ8071A" }, - { 402, "IPQ6018" }, - { 403, "IPQ6028" }, - { 421, "IPQ6000" }, - { 422, "IPQ6010" }, - { 425, "SC7180" }, - { 434, "SM6350" }, - { 439, "SM8350" }, - { 449, "SC8280XP" }, - { 453, "IPQ6005" }, - { 455, "QRB5165" }, - { 457, "SM8450" }, - { 459, "SM7225" }, - { 460, "SA8295P" }, - { 461, "SA8540P" }, - { 480, "SM8450" }, - { 482, "SM8450" }, - { 487, "SC7280" }, - { 495, "SC7180P" }, - { 507, "SM6375" }, + { qcom_board_id(MSM8960) }, + { qcom_board_id(APQ8064) }, + { qcom_board_id(MSM8660A) }, + { qcom_board_id(MSM8260A) }, + { qcom_board_id(APQ8060A) }, + { qcom_board_id(MSM8974) }, + { qcom_board_id(MPQ8064) }, + { qcom_board_id(MSM8960AB) }, + { qcom_board_id(APQ8060AB) }, + { qcom_board_id(MSM8260AB) }, + { qcom_board_id(MSM8660AB) }, + { qcom_board_id(MSM8626) }, + { qcom_board_id(MSM8610) }, + { qcom_board_id(APQ8064AB) }, + { qcom_board_id(MSM8226) }, + { qcom_board_id(MSM8526) }, + { qcom_board_id(MSM8110) }, + { qcom_board_id(MSM8210) }, + { qcom_board_id(MSM8810) }, + { qcom_board_id(MSM8212) }, + { qcom_board_id(MSM8612) }, + { qcom_board_id(MSM8112) }, + { qcom_board_id(MSM8225Q) }, + { qcom_board_id(MSM8625Q) }, + { qcom_board_id(MSM8125Q) }, + { qcom_board_id(APQ8064AA) }, + { qcom_board_id(APQ8084) }, + { qcom_board_id(APQ8074) }, + { qcom_board_id(MSM8274) }, + { qcom_board_id(MSM8674) }, + { qcom_board_id_named(MSM8974PRO_AC, "MSM8974PRO-AC") }, + { qcom_board_id(MSM8126) }, + { qcom_board_id(APQ8026) }, + { qcom_board_id(MSM8926) }, + { qcom_board_id(MSM8326) }, + { qcom_board_id(MSM8916) }, + { qcom_board_id(MSM8956) }, + { qcom_board_id(MSM8976) }, + { qcom_board_id(MSM8994) }, + { qcom_board_id_named(APQ8074PRO_AA, "APQ8074PRO-AA") }, + { qcom_board_id_named(APQ8074PRO_AB, "APQ8074PRO-AB") }, + { qcom_board_id_named(APQ8074PRO_AC, "APQ8074PRO-AC") }, + { qcom_board_id_named(MSM8274PRO_AA, "MSM8274PRO-AA") }, + { qcom_board_id_named(MSM8274PRO_AB, "MSM8274PRO-AB") }, + { qcom_board_id_named(MSM8274PRO_AC, "MSM8274PRO-AC") }, + { qcom_board_id_named(MSM8674PRO_AA, "MSM8674PRO-AA") }, + { qcom_board_id_named(MSM8674PRO_AB, "MSM8674PRO-AB") }, + { qcom_board_id_named(MSM8674PRO_AC, "MSM8674PRO-AC") }, + { qcom_board_id_named(MSM8974PRO_AA, "MSM8974PRO-AA") }, + { qcom_board_id_named(MSM8974PRO_AB, "MSM8974PRO-AB") }, + { qcom_board_id(APQ8028) }, + { qcom_board_id(MSM8128) }, + { qcom_board_id(MSM8228) }, + { qcom_board_id(MSM8528) }, + { qcom_board_id(MSM8628) }, + { qcom_board_id(MSM8928) }, + { qcom_board_id(MSM8510) }, + { qcom_board_id(MSM8512) }, + { qcom_board_id(MSM8936) }, + { qcom_board_id(MSM8939) }, + { qcom_board_id(APQ8036) }, + { qcom_board_id(APQ8039) }, + { qcom_board_id(MSM8996) }, + { qcom_board_id(APQ8016) }, + { qcom_board_id(MSM8216) }, + { qcom_board_id(MSM8116) }, + { qcom_board_id(MSM8616) }, + { qcom_board_id(MSM8992) }, + { qcom_board_id(APQ8094) }, + { qcom_board_id(MDM9607) }, + { qcom_board_id(APQ8096) }, + { qcom_board_id(MSM8998) }, + { qcom_board_id(MSM8953) }, + { qcom_board_id(MDM8207) }, + { qcom_board_id(MDM9207) }, + { qcom_board_id(MDM9307) }, + { qcom_board_id(MDM9628) }, + { qcom_board_id(APQ8053) }, + { qcom_board_id(MSM8996SG) }, + { qcom_board_id(MSM8996AU) }, + { qcom_board_id(APQ8096AU) }, + { qcom_board_id(APQ8096SG) }, + { qcom_board_id(SDM660) }, + { qcom_board_id(SDM630) }, + { qcom_board_id(APQ8098) }, + { qcom_board_id(SDM845) }, + { qcom_board_id(MDM9206) }, + { qcom_board_id(IPQ8074) }, + { qcom_board_id(SDA660) }, + { qcom_board_id(SDM658) }, + { qcom_board_id(SDA658) }, + { qcom_board_id(SDA630) }, + { qcom_board_id(SDM450) }, + { qcom_board_id(SM8150) }, + { qcom_board_id(SDA845) }, + { qcom_board_id(IPQ8072) }, + { qcom_board_id(IPQ8076) }, + { qcom_board_id(IPQ8078) }, + { qcom_board_id(SDM636) }, + { qcom_board_id(SDA636) }, + { qcom_board_id(SDM632) }, + { qcom_board_id(SDA632) }, + { qcom_board_id(SDA450) }, + { qcom_board_id(SM8250) }, + { qcom_board_id(SA8155) }, + { qcom_board_id(IPQ8070) }, + { qcom_board_id(IPQ8071) }, + { qcom_board_id(IPQ8072A) }, + { qcom_board_id(IPQ8074A) }, + { qcom_board_id(IPQ8076A) }, + { qcom_board_id(IPQ8078A) }, + { qcom_board_id(SM6125) }, + { qcom_board_id(IPQ8070A) }, + { qcom_board_id(IPQ8071A) }, + { qcom_board_id(IPQ6018) }, + { qcom_board_id(IPQ6028) }, + { qcom_board_id(SM4250) }, + { qcom_board_id(IPQ6000) }, + { qcom_board_id(IPQ6010) }, + { qcom_board_id(SC7180) }, + { qcom_board_id(SM6350) }, + { qcom_board_id(SM8350) }, + { qcom_board_id(SM6115) }, + { qcom_board_id(SC8280XP) }, + { qcom_board_id(IPQ6005) }, + { qcom_board_id(QRB5165) }, + { qcom_board_id(SM8450) }, + { qcom_board_id(SM8550) }, + { qcom_board_id(SM7225) }, + { qcom_board_id(SA8295P) }, + { qcom_board_id(SA8540P) }, + { qcom_board_id(QCM4290) }, + { qcom_board_id(QCS4290) }, + { qcom_board_id_named(SM8450_2, "SM8450") }, + { qcom_board_id_named(SM8450_3, "SM8450") }, + { qcom_board_id(SC7280) }, + { qcom_board_id(SC7180P) }, + { qcom_board_id(SM6375) }, + { qcom_board_id(QRU1000) }, + { qcom_board_id(QDU1000) }, + { qcom_board_id(QDU1010) }, + { qcom_board_id(QRU1032) }, + { qcom_board_id(QRU1052) }, + { qcom_board_id(QRU1062) }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index 484b42b7454e..a6cbeb40831b 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -98,6 +98,46 @@ static const struct spm_reg_data spm_reg_8916_cpu = { .start_index[PM_SLEEP_MODE_SPC] = 5, }; +static const struct spm_reg_data spm_reg_8939_cpu = { + .reg_offset = spm_reg_offset_v3_0, + .spm_cfg = 0x1, + .spm_dly = 0x3C102800, + .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x50, 0x1B, 0x10, 0x80, + 0x30, 0x90, 0x5B, 0x60, 0x50, 0x03, 0x60, 0x76, 0x76, 0x0B, + 0x50, 0x1B, 0x94, 0x5B, 0x80, 0x10, 0x26, 0x30, 0x50, 0x0F }, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 5, +}; + +static const u16 spm_reg_offset_v2_3[SPM_REG_NR] = { + [SPM_REG_CFG] = 0x08, + [SPM_REG_SPM_CTL] = 0x30, + [SPM_REG_DLY] = 0x34, + [SPM_REG_PMIC_DATA_0] = 0x40, + [SPM_REG_PMIC_DATA_1] = 0x44, +}; + +/* SPM register data for 8976 */ +static const struct spm_reg_data spm_reg_8976_gold_l2 = { + .reg_offset = spm_reg_offset_v2_3, + .spm_cfg = 0x14, + .spm_dly = 0x3c11840a, + .pmic_data[0] = 0x03030080, + .pmic_data[1] = 0x00030000, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 3, +}; + +static const struct spm_reg_data spm_reg_8976_silver_l2 = { + .reg_offset = spm_reg_offset_v2_3, + .spm_cfg = 0x14, + .spm_dly = 0x3c102800, + .pmic_data[0] = 0x03030080, + .pmic_data[1] = 0x00030000, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 2, +}; + static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, [SPM_REG_SPM_CTL] = 0x30, @@ -211,8 +251,14 @@ static const struct of_device_id spm_match_table[] = { .data = &spm_reg_8909_cpu }, { .compatible = "qcom,msm8916-saw2-v3.0-cpu", .data = &spm_reg_8916_cpu }, + { .compatible = "qcom,msm8939-saw2-v3.0-cpu", + .data = &spm_reg_8939_cpu }, { .compatible = "qcom,msm8974-saw2-v2.1-cpu", .data = &spm_reg_8974_8084_cpu }, + { .compatible = "qcom,msm8976-gold-saw2-v2.3-l2", + .data = &spm_reg_8976_gold_l2 }, + { .compatible = "qcom,msm8976-silver-saw2-v2.3-l2", + .data = &spm_reg_8976_silver_l2 }, { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2", .data = &spm_reg_8998_gold_l2 }, { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2", diff --git a/drivers/soc/qcom/trace-rpmh.h b/drivers/soc/qcom/trace-rpmh.h index feb0cb455e37..12b676b20cb2 100644 --- a/drivers/soc/qcom/trace-rpmh.h +++ b/drivers/soc/qcom/trace-rpmh.h @@ -14,16 +14,15 @@ TRACE_EVENT(rpmh_tx_done, - TP_PROTO(struct rsc_drv *d, int m, const struct tcs_request *r, int e), + TP_PROTO(struct rsc_drv *d, int m, const struct tcs_request *r), - TP_ARGS(d, m, r, e), + TP_ARGS(d, m, r), TP_STRUCT__entry( __string(name, d->name) __field(int, m) __field(u32, addr) __field(u32, data) - __field(int, err) ), TP_fast_assign( @@ -31,12 +30,10 @@ TRACE_EVENT(rpmh_tx_done, __entry->m = m; __entry->addr = r->cmds[0].addr; __entry->data = r->cmds[0].data; - __entry->err = e; ), - TP_printk("%s: ack: tcs-m: %d addr: %#x data: %#x errno: %d", - __get_str(name), __entry->m, __entry->addr, __entry->data, - __entry->err) + TP_printk("%s: ack: tcs-m: %d addr: %#x data: %#x", + __get_str(name), __entry->m, __entry->addr, __entry->data) ); TRACE_EVENT(rpmh_send_msg, diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 621ceaa047d4..468ebce1ea88 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -76,6 +76,10 @@ static const struct renesas_family fam_rzv2l __initconst __maybe_unused = { .name = "RZ/V2L", }; +static const struct renesas_family fam_rzv2m __initconst __maybe_unused = { + .name = "RZ/V2M", +}; + static const struct renesas_family fam_shmobile __initconst __maybe_unused = { .name = "SH-Mobile", .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */ @@ -171,6 +175,10 @@ static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = { .id = 0x8447447, }; +static const struct renesas_soc soc_rz_v2m __initconst __maybe_unused = { + .family = &fam_rzv2m, +}; + static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = { .family = &fam_rcar_gen1, }; @@ -380,6 +388,9 @@ static const struct of_device_id renesas_socs[] __initconst = { #if defined(CONFIG_ARCH_R9A07G054) { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, #endif +#if defined(CONFIG_ARCH_R9A09G011) + { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, +#endif #ifdef CONFIG_ARCH_SH73A0 { .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 }, #endif @@ -405,6 +416,11 @@ static const struct renesas_id id_rzg2l __initconst = { .mask = 0xfffffff, }; +static const struct renesas_id id_rzv2m __initconst = { + .offset = 0x104, + .mask = 0xff, +}; + static const struct renesas_id id_prr __initconst = { .offset = 0, .mask = 0xff00, @@ -415,6 +431,7 @@ static const struct of_device_id renesas_ids[] __initconst = { { .compatible = "renesas,r9a07g043-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l }, + { .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m }, { .compatible = "renesas,prr", .data = &id_prr }, { /* sentinel */ } }; @@ -485,6 +502,11 @@ static int __init renesas_soc_init(void) soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", eshi); rev_prefix = "Rev "; + } else if (id == &id_rzv2m) { + eshi = ((product >> 4) & 0x0f); + eslo = product & 0xf; + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u.%u", + eshi, eslo); } if (soc->id && diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 1c171150e878..3684f5b40a80 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -215,20 +215,27 @@ static int __init sifive_ccache_init(void) if (!np) return -ENODEV; - if (of_address_to_resource(np, 0, &res)) - return -ENODEV; + if (of_address_to_resource(np, 0, &res)) { + rc = -ENODEV; + goto err_node_put; + } ccache_base = ioremap(res.start, resource_size(&res)); - if (!ccache_base) - return -ENOMEM; + if (!ccache_base) { + rc = -ENOMEM; + goto err_node_put; + } - if (of_property_read_u32(np, "cache-level", &level)) - return -ENOENT; + if (of_property_read_u32(np, "cache-level", &level)) { + rc = -ENOENT; + goto err_unmap; + } intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { pr_err("No interrupts property\n"); - return -ENODEV; + rc = -ENODEV; + goto err_unmap; } for (i = 0; i < intr_num; i++) { @@ -237,9 +244,10 @@ static int __init sifive_ccache_init(void) NULL); if (rc) { pr_err("Could not request IRQ %d\n", g_irq[i]); - return rc; + goto err_free_irq; } } + of_node_put(np); ccache_config_read(); @@ -250,6 +258,15 @@ static int __init sifive_ccache_init(void) setup_sifive_debug(); #endif return 0; + +err_free_irq: + while (--i >= 0) + free_irq(g_irq[i], NULL); +err_unmap: + iounmap(ccache_base); +err_node_put: + of_node_put(np); + return rc; } device_initcall(sifive_ccache_init); diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index d1ecadffa1bb..5f5324294636 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -143,6 +143,7 @@ config SOC_TEGRA_FLOWCTRL config SOC_TEGRA_PMC bool select GENERIC_PINCONF + select IRQ_DOMAIN_HIERARCHY select PM_OPP select PM_GENERIC_DOMAINS select REGMAP diff --git a/drivers/soc/tegra/cbb/tegra-cbb.c b/drivers/soc/tegra/cbb/tegra-cbb.c index d200937353c7..a8566b9dd8de 100644 --- a/drivers/soc/tegra/cbb/tegra-cbb.c +++ b/drivers/soc/tegra/cbb/tegra-cbb.c @@ -72,18 +72,7 @@ static int tegra_cbb_err_show(struct seq_file *file, void *data) return cbb->ops->debugfs_show(cbb, file, data); } - -static int tegra_cbb_err_open(struct inode *inode, struct file *file) -{ - return single_open(file, tegra_cbb_err_show, inode->i_private); -} - -static const struct file_operations tegra_cbb_err_fops = { - .open = tegra_cbb_err_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release -}; +DEFINE_SHOW_ATTRIBUTE(tegra_cbb_err); static int tegra_cbb_err_debugfs_init(struct tegra_cbb *cbb) { diff --git a/drivers/soc/tegra/cbb/tegra194-cbb.c b/drivers/soc/tegra/cbb/tegra194-cbb.c index 1ae0bd9a1ac1..d4112b683f00 100644 --- a/drivers/soc/tegra/cbb/tegra194-cbb.c +++ b/drivers/soc/tegra/cbb/tegra194-cbb.c @@ -102,8 +102,6 @@ #define CLUSTER_NOC_VQC GENMASK(17, 16) #define CLUSTER_NOC_MSTR_ID GENMASK(21, 18) -#define USRBITS_MSTR_ID GENMASK(21, 18) - #define CBB_ERR_OPC GENMASK(4, 1) #define CBB_ERR_ERRCODE GENMASK(10, 8) #define CBB_ERR_LEN1 GENMASK(27, 16) @@ -2038,15 +2036,17 @@ static irqreturn_t tegra194_cbb_err_isr(int irq, void *data) smp_processor_id(), priv->noc->name, priv->res->start, irq); - mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->errlog5) - 1; is_fatal = print_errlog(NULL, priv, status); /* - * If illegal request is from CCPLEX(0x1) - * initiator then call BUG() to crash system. + * If illegal request is from CCPLEX(0x1) initiator + * and error is fatal then call BUG() to crash system. */ - if ((mstr_id == 0x1) && priv->noc->erd_mask_inband_err) - is_inband_err = 1; + if (priv->noc->erd_mask_inband_err) { + mstr_id = FIELD_GET(CBB_NOC_MSTR_ID, priv->errlog5); + if (mstr_id == 0x1) + is_inband_err = 1; + } } } @@ -2226,10 +2226,8 @@ static int tegra194_cbb_get_bridges(struct tegra194_cbb *cbb, struct device_node cbb->bridges[i].base = devm_ioremap_resource(cbb->base.dev, &cbb->bridges[i].res); - if (IS_ERR(cbb->bridges[i].base)) { - dev_err(cbb->base.dev, "failed to map AXI2APB range\n"); + if (IS_ERR(cbb->bridges[i].base)) return PTR_ERR(cbb->bridges[i].base); - } } } diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c index 3528f9e15d5c..f33d094e5ea6 100644 --- a/drivers/soc/tegra/cbb/tegra234-cbb.c +++ b/drivers/soc/tegra/cbb/tegra234-cbb.c @@ -72,6 +72,11 @@ #define REQ_SOCKET_ID GENMASK(27, 24) +#define CCPLEX_MSTRID 0x1 +#define FIREWALL_APERTURE_SZ 0x10000 +/* Write firewall check enable */ +#define WEN 0x20000 + enum tegra234_cbb_fabric_ids { CBB_FAB_ID, SCE_FAB_ID, @@ -92,11 +97,15 @@ struct tegra234_slave_lookup { struct tegra234_cbb_fabric { const char *name; phys_addr_t off_mask_erd; - bool erd_mask_inband_err; + phys_addr_t firewall_base; + unsigned int firewall_ctl; + unsigned int firewall_wr_ctl; const char * const *master_id; unsigned int notifier_offset; const struct tegra_cbb_error *errors; + const int max_errors; const struct tegra234_slave_lookup *slave_map; + const int max_slaves; }; struct tegra234_cbb { @@ -128,6 +137,44 @@ static inline struct tegra234_cbb *to_tegra234_cbb(struct tegra_cbb *cbb) static LIST_HEAD(cbb_list); static DEFINE_SPINLOCK(cbb_lock); +static bool +tegra234_cbb_write_access_allowed(struct platform_device *pdev, struct tegra234_cbb *cbb) +{ + u32 val; + + if (!cbb->fabric->firewall_base || + !cbb->fabric->firewall_ctl || + !cbb->fabric->firewall_wr_ctl) { + dev_info(&pdev->dev, "SoC data missing for firewall\n"); + return false; + } + + if ((cbb->fabric->firewall_ctl > FIREWALL_APERTURE_SZ) || + (cbb->fabric->firewall_wr_ctl > FIREWALL_APERTURE_SZ)) { + dev_err(&pdev->dev, "wrong firewall offset value\n"); + return false; + } + + val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_ctl); + /* + * If the firewall check feature for allowing or blocking the + * write accesses through the firewall of a fabric is disabled + * then CCPLEX can write to the registers of that fabric. + */ + if (!(val & WEN)) + return true; + + /* + * If the firewall check is enabled then check whether CCPLEX + * has write access to the fabric's error notifier registers + */ + val = readl(cbb->regs + cbb->fabric->firewall_base + cbb->fabric->firewall_wr_ctl); + if (val & (BIT(CCPLEX_MSTRID))) + return true; + + return false; +} + static void tegra234_cbb_fault_enable(struct tegra_cbb *cbb) { struct tegra234_cbb *priv = to_tegra234_cbb(cbb); @@ -271,6 +318,12 @@ static void tegra234_cbb_print_error(struct seq_file *file, struct tegra234_cbb tegra_cbb_print_err(file, "\t Multiple type of errors reported\n"); while (status) { + if (type >= cbb->fabric->max_errors) { + tegra_cbb_print_err(file, "\t Wrong type index:%u, status:%u\n", + type, status); + return; + } + if (status & 0x1) tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n", cbb->fabric->errors[type].code); @@ -282,6 +335,12 @@ static void tegra234_cbb_print_error(struct seq_file *file, struct tegra234_cbb type = 0; while (overflow) { + if (type >= cbb->fabric->max_errors) { + tegra_cbb_print_err(file, "\t Wrong type index:%u, overflow:%u\n", + type, overflow); + return; + } + if (overflow & 0x1) tegra_cbb_print_err(file, "\t Overflow\t\t: Multiple %s\n", cbb->fabric->errors[type].code); @@ -334,8 +393,11 @@ static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb) access_type = FIELD_GET(FAB_EM_EL_ACCESSTYPE, cbb->mn_attr0); tegra_cbb_print_err(file, "\n"); - tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n", - cbb->fabric->errors[cbb->type].code); + if (cbb->type < cbb->fabric->max_errors) + tegra_cbb_print_err(file, "\t Error Code\t\t: %s\n", + cbb->fabric->errors[cbb->type].code); + else + tegra_cbb_print_err(file, "\t Wrong type index:%u\n", cbb->type); tegra_cbb_print_err(file, "\t MASTER_ID\t\t: %s\n", cbb->fabric->master_id[mstr_id]); tegra_cbb_print_err(file, "\t Address\t\t: %#llx\n", cbb->access); @@ -374,6 +436,11 @@ static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb) if ((fab_id == PSC_FAB_ID) || (fab_id == FSI_FAB_ID)) return; + if (slave_id >= cbb->fabric->max_slaves) { + tegra_cbb_print_err(file, "\t Invalid slave_id:%d\n", slave_id); + return; + } + if (!strcmp(cbb->fabric->errors[cbb->type].code, "TIMEOUT_ERR")) { tegra234_lookup_slave_timeout(file, cbb, slave_id, fab_id); return; @@ -517,7 +584,7 @@ static irqreturn_t tegra234_cbb_isr(int irq, void *data) u32 status = tegra_cbb_get_status(cbb); if (status && (irq == priv->sec_irq)) { - tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@%llx, irq=%d\n", + tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@0x%llx, irq=%d\n", smp_processor_id(), priv->fabric->name, priv->res->start, irq); @@ -525,14 +592,14 @@ static irqreturn_t tegra234_cbb_isr(int irq, void *data) if (err) goto unlock; - mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->mn_user_bits); - /* - * If illegal request is from CCPLEX(id:0x1) master then call BUG() to - * crash system. + * If illegal request is from CCPLEX(id:0x1) master then call WARN() */ - if ((mstr_id == 0x1) && priv->fabric->off_mask_erd) - is_inband_err = 1; + if (priv->fabric->off_mask_erd) { + mstr_id = FIELD_GET(USRBITS_MSTR_ID, priv->mn_user_bits); + if (mstr_id == CCPLEX_MSTRID) + is_inband_err = 1; + } } } @@ -640,8 +707,13 @@ static const struct tegra234_cbb_fabric tegra234_aon_fabric = { .name = "aon-fabric", .master_id = tegra234_master_id, .slave_map = tegra234_aon_slave_map, + .max_slaves = ARRAY_SIZE(tegra234_aon_slave_map), .errors = tegra234_cbb_errors, + .max_errors = ARRAY_SIZE(tegra234_cbb_errors), .notifier_offset = 0x17000, + .firewall_base = 0x30000, + .firewall_ctl = 0x8d0, + .firewall_wr_ctl = 0x8c8, }; static const struct tegra234_slave_lookup tegra234_bpmp_slave_map[] = { @@ -656,8 +728,13 @@ static const struct tegra234_cbb_fabric tegra234_bpmp_fabric = { .name = "bpmp-fabric", .master_id = tegra234_master_id, .slave_map = tegra234_bpmp_slave_map, + .max_slaves = ARRAY_SIZE(tegra234_bpmp_slave_map), .errors = tegra234_cbb_errors, + .max_errors = ARRAY_SIZE(tegra234_cbb_errors), .notifier_offset = 0x19000, + .firewall_base = 0x30000, + .firewall_ctl = 0x8f0, + .firewall_wr_ctl = 0x8e8, }; static const struct tegra234_slave_lookup tegra234_cbb_slave_map[] = { @@ -728,55 +805,62 @@ static const struct tegra234_cbb_fabric tegra234_cbb_fabric = { .name = "cbb-fabric", .master_id = tegra234_master_id, .slave_map = tegra234_cbb_slave_map, + .max_slaves = ARRAY_SIZE(tegra234_cbb_slave_map), .errors = tegra234_cbb_errors, + .max_errors = ARRAY_SIZE(tegra234_cbb_errors), .notifier_offset = 0x60000, - .off_mask_erd = 0x3a004 + .off_mask_erd = 0x3a004, + .firewall_base = 0x10000, + .firewall_ctl = 0x23f0, + .firewall_wr_ctl = 0x23e8, }; -static const struct tegra234_slave_lookup tegra234_dce_slave_map[] = { +static const struct tegra234_slave_lookup tegra234_common_slave_map[] = { { "AXI2APB", 0x00000 }, { "AST0", 0x15000 }, { "AST1", 0x16000 }, + { "CBB", 0x17000 }, + { "RSVD", 0x00000 }, { "CPU", 0x18000 }, }; static const struct tegra234_cbb_fabric tegra234_dce_fabric = { .name = "dce-fabric", .master_id = tegra234_master_id, - .slave_map = tegra234_dce_slave_map, + .slave_map = tegra234_common_slave_map, + .max_slaves = ARRAY_SIZE(tegra234_common_slave_map), .errors = tegra234_cbb_errors, + .max_errors = ARRAY_SIZE(tegra234_cbb_errors), .notifier_offset = 0x19000, -}; - -static const struct tegra234_slave_lookup tegra234_rce_slave_map[] = { - { "AXI2APB", 0x00000 }, - { "AST0", 0x15000 }, - { "AST1", 0x16000 }, - { "CPU", 0x18000 }, + .firewall_base = 0x30000, + .firewall_ctl = 0x290, + .firewall_wr_ctl = 0x288, }; static const struct tegra234_cbb_fabric tegra234_rce_fabric = { .name = "rce-fabric", .master_id = tegra234_master_id, - .slave_map = tegra234_rce_slave_map, + .slave_map = tegra234_common_slave_map, + .max_slaves = ARRAY_SIZE(tegra234_common_slave_map), .errors = tegra234_cbb_errors, + .max_errors = ARRAY_SIZE(tegra234_cbb_errors), .notifier_offset = 0x19000, -}; - -static const struct tegra234_slave_lookup tegra234_sce_slave_map[] = { - { "AXI2APB", 0x00000 }, - { "AST0", 0x15000 }, - { "AST1", 0x16000 }, - { "CBB", 0x17000 }, - { "CPU", 0x18000 }, + .firewall_base = 0x30000, + .firewall_ctl = 0x290, + .firewall_wr_ctl = 0x288, }; static const struct tegra234_cbb_fabric tegra234_sce_fabric = { .name = "sce-fabric", .master_id = tegra234_master_id, - .slave_map = tegra234_sce_slave_map, + .slave_map = tegra234_common_slave_map, + .max_slaves = ARRAY_SIZE(tegra234_common_slave_map), .errors = tegra234_cbb_errors, + .max_errors = ARRAY_SIZE(tegra234_cbb_errors), .notifier_offset = 0x19000, + .firewall_base = 0x30000, + .firewall_ctl = 0x290, + .firewall_wr_ctl = 0x288, }; static const char * const tegra241_master_id[] = { @@ -889,7 +973,7 @@ static const struct tegra_cbb_error tegra241_cbb_errors[] = { }; static const struct tegra234_slave_lookup tegra241_cbb_slave_map[] = { - { "CCPLEX", 0x50000 }, + { "RSVD", 0x00000 }, { "PCIE_C8", 0x51000 }, { "PCIE_C9", 0x52000 }, { "RSVD", 0x00000 }, @@ -942,22 +1026,32 @@ static const struct tegra234_slave_lookup tegra241_cbb_slave_map[] = { { "PCIE_C3", 0x58000 }, { "PCIE_C0", 0x59000 }, { "PCIE_C1", 0x5a000 }, + { "CCPLEX", 0x50000 }, { "AXI2APB_29", 0x85000 }, { "AXI2APB_30", 0x86000 }, + { "CBB_CENTRAL", 0x00000 }, + { "AXI2APB_31", 0x8E000 }, + { "AXI2APB_32", 0x8F000 }, }; static const struct tegra234_cbb_fabric tegra241_cbb_fabric = { .name = "cbb-fabric", .master_id = tegra241_master_id, .slave_map = tegra241_cbb_slave_map, + .max_slaves = ARRAY_SIZE(tegra241_cbb_slave_map), .errors = tegra241_cbb_errors, + .max_errors = ARRAY_SIZE(tegra241_cbb_errors), .notifier_offset = 0x60000, .off_mask_erd = 0x40004, + .firewall_base = 0x20000, + .firewall_ctl = 0x2370, + .firewall_wr_ctl = 0x2368, }; static const struct tegra234_slave_lookup tegra241_bpmp_slave_map[] = { { "RSVD", 0x00000 }, { "RSVD", 0x00000 }, + { "RSVD", 0x00000 }, { "CBB", 0x15000 }, { "CPU", 0x16000 }, { "AXI2APB", 0x00000 }, @@ -969,8 +1063,13 @@ static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = { .name = "bpmp-fabric", .master_id = tegra241_master_id, .slave_map = tegra241_bpmp_slave_map, + .max_slaves = ARRAY_SIZE(tegra241_bpmp_slave_map), .errors = tegra241_cbb_errors, + .max_errors = ARRAY_SIZE(tegra241_cbb_errors), .notifier_offset = 0x19000, + .firewall_base = 0x30000, + .firewall_ctl = 0x8f0, + .firewall_wr_ctl = 0x8e8, }; static const struct of_device_id tegra234_cbb_dt_ids[] = { @@ -1055,6 +1154,15 @@ static int tegra234_cbb_probe(struct platform_device *pdev) platform_set_drvdata(pdev, cbb); + /* + * Don't enable error reporting for a Fabric if write to it's registers + * is blocked by CBB firewall. + */ + if (!tegra234_cbb_write_access_allowed(pdev, cbb)) { + dev_info(&pdev->dev, "error reporting not enabled due to firewall\n"); + return 0; + } + spin_lock_irqsave(&cbb_lock, flags); list_add(&cbb->base.node, &cbb_list); spin_unlock_irqrestore(&cbb_lock, flags); diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 6542267a224d..f02953f793e9 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -35,6 +35,19 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { [TEGRA_REVISION_A04] = "A04", }; +static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = { + [TEGRA_PLATFORM_SILICON] = "Silicon", + [TEGRA_PLATFORM_QT] = "QT", + [TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA", + [TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA", + [TEGRA_PLATFORM_ASIM_QT] = "Asim QT", + [TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim", + [TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim", + [TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation", + [TEGRA_PLATFORM_VDK] = "VDK", + [TEGRA_PLATFORM_VSP] = "VSP", +}; + static const struct of_device_id car_match[] __initconst = { { .compatible = "nvidia,tegra20-car", }, { .compatible = "nvidia,tegra30-car", }, @@ -94,112 +107,6 @@ static int tegra_fuse_read(void *priv, unsigned int offset, void *value, return 0; } -static const struct nvmem_cell_info tegra_fuse_cells[] = { - { - .name = "tsensor-cpu1", - .offset = 0x084, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "tsensor-cpu2", - .offset = 0x088, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "tsensor-cpu0", - .offset = 0x098, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "xusb-pad-calibration", - .offset = 0x0f0, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "tsensor-cpu3", - .offset = 0x12c, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "sata-calibration", - .offset = 0x124, - .bytes = 1, - .bit_offset = 0, - .nbits = 2, - }, { - .name = "tsensor-gpu", - .offset = 0x154, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "tsensor-mem0", - .offset = 0x158, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "tsensor-mem1", - .offset = 0x15c, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "tsensor-pllx", - .offset = 0x160, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "tsensor-common", - .offset = 0x180, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "gpu-gcplex-config-fuse", - .offset = 0x1c8, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "tsensor-realignment", - .offset = 0x1fc, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "gpu-calibration", - .offset = 0x204, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "xusb-pad-calibration-ext", - .offset = 0x250, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "gpu-pdi0", - .offset = 0x300, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, { - .name = "gpu-pdi1", - .offset = 0x304, - .bytes = 4, - .bit_offset = 0, - .nbits = 32, - }, -}; - static void tegra_fuse_restore(void *base) { fuse->base = (void __iomem *)base; @@ -253,8 +160,10 @@ static int tegra_fuse_probe(struct platform_device *pdev) nvmem.name = "fuse"; nvmem.id = -1; nvmem.owner = THIS_MODULE; - nvmem.cells = tegra_fuse_cells; - nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells); + nvmem.cells = fuse->soc->cells; + nvmem.ncells = fuse->soc->num_cells; + nvmem.keepout = fuse->soc->keepouts; + nvmem.nkeepout = fuse->soc->num_keepouts; nvmem.type = NVMEM_TYPE_OTP; nvmem.read_only = true; nvmem.root_only = true; @@ -474,8 +383,13 @@ struct device * __init tegra_soc_device_register(void) return NULL; attr->family = kasprintf(GFP_KERNEL, "Tegra"); - attr->revision = kasprintf(GFP_KERNEL, "%s", - tegra_revision_name[tegra_sku_info.revision]); + if (tegra_is_silicon()) + attr->revision = kasprintf(GFP_KERNEL, "%s %s", + tegra_platform_name[tegra_sku_info.platform], + tegra_revision_name[tegra_sku_info.revision]); + else + attr->revision = kasprintf(GFP_KERNEL, "%s", + tegra_platform_name[tegra_sku_info.platform]); attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); attr->custom_attr_group = fuse->soc->soc_attr_group; diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index f01d8a2547b6..932a03c64534 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -9,6 +9,7 @@ #include <linux/io.h> #include <linux/kernel.h> #include <linux/nvmem-consumer.h> +#include <linux/nvmem-provider.h> #include <linux/of_device.h> #include <linux/of_address.h> #include <linux/platform_device.h> @@ -133,6 +134,82 @@ const struct tegra_fuse_soc tegra114_fuse_soc = { #endif #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) +static const struct nvmem_cell_info tegra124_fuse_cells[] = { + { + .name = "tsensor-cpu1", + .offset = 0x084, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu2", + .offset = 0x088, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu0", + .offset = 0x098, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "xusb-pad-calibration", + .offset = 0x0f0, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu3", + .offset = 0x12c, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "sata-calibration", + .offset = 0x124, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-gpu", + .offset = 0x154, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-mem0", + .offset = 0x158, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-mem1", + .offset = 0x15c, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-pllx", + .offset = 0x160, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-common", + .offset = 0x180, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-realignment", + .offset = 0x1fc, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, +}; + static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = { { .nvmem_name = "fuse", @@ -209,12 +286,96 @@ const struct tegra_fuse_soc tegra124_fuse_soc = { .info = &tegra124_fuse_info, .lookups = tegra124_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra124_fuse_lookups), + .cells = tegra124_fuse_cells, + .num_cells = ARRAY_SIZE(tegra124_fuse_cells), .soc_attr_group = &tegra_soc_attr_group, .clk_suspend_on = true, }; #endif #if defined(CONFIG_ARCH_TEGRA_210_SOC) +static const struct nvmem_cell_info tegra210_fuse_cells[] = { + { + .name = "tsensor-cpu1", + .offset = 0x084, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu2", + .offset = 0x088, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu0", + .offset = 0x098, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "xusb-pad-calibration", + .offset = 0x0f0, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu3", + .offset = 0x12c, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "sata-calibration", + .offset = 0x124, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-gpu", + .offset = 0x154, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-mem0", + .offset = 0x158, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-mem1", + .offset = 0x15c, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-pllx", + .offset = 0x160, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-common", + .offset = 0x180, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "gpu-calibration", + .offset = 0x204, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "xusb-pad-calibration-ext", + .offset = 0x250, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, +}; + static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = { { .nvmem_name = "fuse", @@ -295,6 +456,8 @@ const struct tegra_fuse_soc tegra210_fuse_soc = { .speedo_init = tegra210_init_speedo_data, .info = &tegra210_fuse_info, .lookups = tegra210_fuse_lookups, + .cells = tegra210_fuse_cells, + .num_cells = ARRAY_SIZE(tegra210_fuse_cells), .num_lookups = ARRAY_SIZE(tegra210_fuse_lookups), .soc_attr_group = &tegra_soc_attr_group, .clk_suspend_on = false, @@ -302,6 +465,22 @@ const struct tegra_fuse_soc tegra210_fuse_soc = { #endif #if defined(CONFIG_ARCH_TEGRA_186_SOC) +static const struct nvmem_cell_info tegra186_fuse_cells[] = { + { + .name = "xusb-pad-calibration", + .offset = 0x0f0, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "xusb-pad-calibration-ext", + .offset = 0x250, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, +}; + static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = { { .nvmem_name = "fuse", @@ -316,9 +495,17 @@ static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = { }, }; +static const struct nvmem_keepout tegra186_fuse_keepouts[] = { + { .start = 0x01c, .end = 0x0f0 }, + { .start = 0x138, .end = 0x198 }, + { .start = 0x1d8, .end = 0x250 }, + { .start = 0x280, .end = 0x290 }, + { .start = 0x340, .end = 0x344 } +}; + static const struct tegra_fuse_info tegra186_fuse_info = { .read = tegra30_fuse_read, - .size = 0x300, + .size = 0x478, .spare = 0x280, }; @@ -327,12 +514,50 @@ const struct tegra_fuse_soc tegra186_fuse_soc = { .info = &tegra186_fuse_info, .lookups = tegra186_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra186_fuse_lookups), + .cells = tegra186_fuse_cells, + .num_cells = ARRAY_SIZE(tegra186_fuse_cells), + .keepouts = tegra186_fuse_keepouts, + .num_keepouts = ARRAY_SIZE(tegra186_fuse_keepouts), .soc_attr_group = &tegra_soc_attr_group, .clk_suspend_on = false, }; #endif #if defined(CONFIG_ARCH_TEGRA_194_SOC) +static const struct nvmem_cell_info tegra194_fuse_cells[] = { + { + .name = "xusb-pad-calibration", + .offset = 0x0f0, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "gpu-gcplex-config-fuse", + .offset = 0x1c8, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "xusb-pad-calibration-ext", + .offset = 0x250, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "gpu-pdi0", + .offset = 0x300, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "gpu-pdi1", + .offset = 0x304, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, +}; + static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { { .nvmem_name = "fuse", @@ -362,9 +587,18 @@ static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { }, }; +static const struct nvmem_keepout tegra194_fuse_keepouts[] = { + { .start = 0x01c, .end = 0x0b8 }, + { .start = 0x12c, .end = 0x198 }, + { .start = 0x1a0, .end = 0x1bc }, + { .start = 0x1d8, .end = 0x250 }, + { .start = 0x270, .end = 0x290 }, + { .start = 0x310, .end = 0x45c } +}; + static const struct tegra_fuse_info tegra194_fuse_info = { .read = tegra30_fuse_read, - .size = 0x300, + .size = 0x650, .spare = 0x280, }; @@ -373,12 +607,32 @@ const struct tegra_fuse_soc tegra194_fuse_soc = { .info = &tegra194_fuse_info, .lookups = tegra194_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra194_fuse_lookups), + .cells = tegra194_fuse_cells, + .num_cells = ARRAY_SIZE(tegra194_fuse_cells), + .keepouts = tegra194_fuse_keepouts, + .num_keepouts = ARRAY_SIZE(tegra194_fuse_keepouts), .soc_attr_group = &tegra194_soc_attr_group, .clk_suspend_on = false, }; #endif #if defined(CONFIG_ARCH_TEGRA_234_SOC) +static const struct nvmem_cell_info tegra234_fuse_cells[] = { + { + .name = "xusb-pad-calibration", + .offset = 0x0f0, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "xusb-pad-calibration-ext", + .offset = 0x250, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, +}; + static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = { { .nvmem_name = "fuse", @@ -393,9 +647,23 @@ static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = { }, }; +static const struct nvmem_keepout tegra234_fuse_keepouts[] = { + { .start = 0x01c, .end = 0x0c8 }, + { .start = 0x12c, .end = 0x184 }, + { .start = 0x190, .end = 0x198 }, + { .start = 0x1a0, .end = 0x204 }, + { .start = 0x21c, .end = 0x250 }, + { .start = 0x25c, .end = 0x2f0 }, + { .start = 0x310, .end = 0x3d8 }, + { .start = 0x400, .end = 0x4f0 }, + { .start = 0x4f8, .end = 0x7e8 }, + { .start = 0x8d0, .end = 0x8d8 }, + { .start = 0xacc, .end = 0xf00 } +}; + static const struct tegra_fuse_info tegra234_fuse_info = { .read = tegra30_fuse_read, - .size = 0x300, + .size = 0x98c, .spare = 0x280, }; @@ -404,6 +672,10 @@ const struct tegra_fuse_soc tegra234_fuse_soc = { .info = &tegra234_fuse_info, .lookups = tegra234_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra234_fuse_lookups), + .cells = tegra234_fuse_cells, + .num_cells = ARRAY_SIZE(tegra234_fuse_cells), + .keepouts = tegra234_fuse_keepouts, + .num_keepouts = ARRAY_SIZE(tegra234_fuse_keepouts), .soc_attr_group = &tegra194_soc_attr_group, .clk_suspend_on = false, }; diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h index 2bb1f9d6a6e6..90f23be73894 100644 --- a/drivers/soc/tegra/fuse/fuse.h +++ b/drivers/soc/tegra/fuse/fuse.h @@ -32,6 +32,10 @@ struct tegra_fuse_soc { const struct nvmem_cell_lookup *lookups; unsigned int num_lookups; + const struct nvmem_cell_info *cells; + unsigned int num_cells; + const struct nvmem_keepout *keepouts; + unsigned int num_keepouts; const struct attribute_group *soc_attr_group; diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 3351bd872ab2..4591c5bcb690 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -156,6 +156,7 @@ void __init tegra_init_revision(void) } tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO); + tegra_sku_info.platform = tegra_get_platform(); } void __init tegra_init_apbmisc(void) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 678e8bc8a45d..cf4cfbf9f7c5 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -23,6 +23,7 @@ #include <linux/err.h> #include <linux/export.h> #include <linux/init.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/irqdomain.h> @@ -46,6 +47,7 @@ #include <linux/seq_file.h> #include <linux/slab.h> #include <linux/spinlock.h> +#include <linux/syscore_ops.h> #include <soc/tegra/common.h> #include <soc/tegra/fuse.h> @@ -182,6 +184,9 @@ #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) +#define WAKE_AOWAKE_SW_STATUS_W_0 0x49c +#define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2)) +#define WAKE_LATCH_SW 0x498 #define WAKE_AOWAKE_CTRL 0x4f4 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) @@ -269,16 +274,14 @@ struct tegra_powergate { struct tegra_io_pad_soc { enum tegra_io_pad id; unsigned int dpd; + unsigned int request; + unsigned int status; unsigned int voltage; const char *name; }; struct tegra_pmc_regs { unsigned int scratch0; - unsigned int dpd_req; - unsigned int dpd_status; - unsigned int dpd2_req; - unsigned int dpd2_status; unsigned int rst_status; unsigned int rst_source_shift; unsigned int rst_source_mask; @@ -369,6 +372,8 @@ struct tegra_pmc_soc { */ const struct tegra_wake_event *wake_events; unsigned int num_wake_events; + unsigned int max_wake_events; + unsigned int max_wake_vectors; const struct pmc_clk_init_data *pmc_clks_data; unsigned int num_pmc_clks; @@ -409,6 +414,11 @@ struct tegra_pmc_soc { * @clk_nb: pclk clock changes handler * @core_domain_state_synced: flag marking the core domain's state as synced * @core_domain_registered: flag marking the core domain as registered + * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes + * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not + * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask + * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in + * cntrl register associated with each wake during system suspend. */ struct tegra_pmc { struct device *dev; @@ -449,6 +459,12 @@ struct tegra_pmc { bool core_domain_state_synced; bool core_domain_registered; + + unsigned long *wake_type_level_map; + unsigned long *wake_type_dual_edge_map; + unsigned long *wake_sw_status_map; + unsigned long *wake_cntrl_level_map; + struct syscore_ops syscore; }; static struct tegra_pmc *pmc = &(struct tegra_pmc) { @@ -1540,46 +1556,20 @@ tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) return NULL; } -static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, - enum tegra_io_pad id, - unsigned long *request, - unsigned long *status, - u32 *mask) -{ - const struct tegra_io_pad_soc *pad; - - pad = tegra_io_pad_find(pmc, id); - if (!pad) { - dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); - return -ENOENT; - } - - if (pad->dpd == UINT_MAX) - return -ENOTSUPP; - - *mask = BIT(pad->dpd % 32); - - if (pad->dpd < 32) { - *status = pmc->soc->regs->dpd_status; - *request = pmc->soc->regs->dpd_req; - } else { - *status = pmc->soc->regs->dpd2_status; - *request = pmc->soc->regs->dpd2_req; - } - - return 0; -} - -static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, - unsigned long *request, unsigned long *status, +static int tegra_io_pad_prepare(struct tegra_pmc *pmc, + const struct tegra_io_pad_soc *pad, + unsigned long *request, + unsigned long *status, u32 *mask) { unsigned long rate, value; - int err; - err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); - if (err) - return err; + if (pad->dpd == UINT_MAX) + return -EINVAL; + + *request = pad->request; + *status = pad->status; + *mask = BIT(pad->dpd); if (pmc->clk) { rate = pmc->rate; @@ -1631,13 +1621,20 @@ static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) */ int tegra_io_pad_power_enable(enum tegra_io_pad id) { + const struct tegra_io_pad_soc *pad; unsigned long request, status; u32 mask; int err; + pad = tegra_io_pad_find(pmc, id); + if (!pad) { + dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); + return -ENOENT; + } + mutex_lock(&pmc->powergates_lock); - err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); + err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); if (err < 0) { dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); goto unlock; @@ -1667,13 +1664,20 @@ EXPORT_SYMBOL(tegra_io_pad_power_enable); */ int tegra_io_pad_power_disable(enum tegra_io_pad id) { + const struct tegra_io_pad_soc *pad; unsigned long request, status; u32 mask; int err; + pad = tegra_io_pad_find(pmc, id); + if (!pad) { + dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); + return -ENOENT; + } + mutex_lock(&pmc->powergates_lock); - err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); + err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); if (err < 0) { dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); goto unlock; @@ -1697,14 +1701,21 @@ EXPORT_SYMBOL(tegra_io_pad_power_disable); static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) { - unsigned long request, status; + const struct tegra_io_pad_soc *pad; + unsigned long status; u32 mask, value; - int err; - err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, - &mask); - if (err) - return err; + pad = tegra_io_pad_find(pmc, id); + if (!pad) { + dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); + return -ENOENT; + } + + if (pad->dpd == UINT_MAX) + return -EINVAL; + + status = pad->status; + mask = BIT(pad->dpd); value = tegra_pmc_readl(pmc, status); @@ -1930,10 +1941,30 @@ static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) return 0; } -static void tegra_pmc_init(struct tegra_pmc *pmc) +static int tegra_pmc_init(struct tegra_pmc *pmc) { + if (pmc->soc->max_wake_events > 0) { + pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); + if (!pmc->wake_type_level_map) + return -ENOMEM; + + pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); + if (!pmc->wake_type_dual_edge_map) + return -ENOMEM; + + pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); + if (!pmc->wake_sw_status_map) + return -ENOMEM; + + pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); + if (!pmc->wake_cntrl_level_map) + return -ENOMEM; + } + if (pmc->soc->init) pmc->soc->init(pmc); + + return 0; } static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) @@ -2424,15 +2455,21 @@ static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: value |= WAKE_AOWAKE_CNTRL_LEVEL; + set_bit(data->hwirq, pmc->wake_type_level_map); + clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); break; case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: value &= ~WAKE_AOWAKE_CNTRL_LEVEL; + clear_bit(data->hwirq, pmc->wake_type_level_map); + clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); break; case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: value ^= WAKE_AOWAKE_CNTRL_LEVEL; + clear_bit(data->hwirq, pmc->wake_type_level_map); + set_bit(data->hwirq, pmc->wake_type_dual_edge_map); break; default: @@ -2964,7 +3001,11 @@ static int tegra_pmc_probe(struct platform_device *pdev) pmc->dev = &pdev->dev; - tegra_pmc_init(pmc); + err = tegra_pmc_init(pmc); + if (err < 0) { + dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); + return err; + } tegra_pmc_init_tsense_reset(pmc); @@ -3015,6 +3056,156 @@ cleanup_sysfs: return err; } +/* + * Ensures that sufficient time is passed for a register write to + * serialize into the 32KHz domain. + */ +static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) +{ + writel(value, pmc->wake + offset); + udelay(130); +} + +static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) +{ + unsigned int offset = WAKE_AOWAKE_CNTRL(wake); + u32 value; + + value = readl(pmc->wake + offset); + if (level) + value |= WAKE_AOWAKE_CNTRL_LEVEL; + else + value &= ~WAKE_AOWAKE_CNTRL_LEVEL; + + writel(value, pmc->wake + offset); +} + +static void wke_write_wake_levels(struct tegra_pmc *pmc) +{ + unsigned int i; + + for (i = 0; i < pmc->soc->max_wake_events; i++) + wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); +} + +static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) +{ + wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0); +} + +static void wke_read_sw_wake_status(struct tegra_pmc *pmc) +{ + unsigned long status; + unsigned int wake, i; + + for (i = 0; i < pmc->soc->max_wake_events; i++) + wke_write_wake_level(pmc, i, 0); + + wke_clear_sw_wake_status(pmc); + + wke_32kwritel(pmc, 1, WAKE_LATCH_SW); + + /* + * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to + * obtain the current status of the input wake signals, change + * the polarity of the wake level from 0->1 while latching to force + * a positive edge if the sampled signal is '1'. + */ + for (i = 0; i < pmc->soc->max_wake_events; i++) + wke_write_wake_level(pmc, i, 1); + + /* + * Wait for the update to be synced into the 32kHz domain, + * and let enough time lapse, so that the wake signals have time to + * be sampled. + */ + udelay(300); + + wke_32kwritel(pmc, 0, WAKE_LATCH_SW); + + bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); + + for (i = 0; i < pmc->soc->max_wake_vectors; i++) { + status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); + + for_each_set_bit(wake, &status, 32) + set_bit(wake + (i * 32), pmc->wake_sw_status_map); + } +} + +static void wke_clear_wake_status(struct tegra_pmc *pmc) +{ + unsigned long status; + unsigned int i, wake; + u32 mask; + + for (i = 0; i < pmc->soc->max_wake_vectors; i++) { + mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); + status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; + + for_each_set_bit(wake, &status, 32) + wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake)); + } +} + +/* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */ +static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index, + unsigned long status) +{ + unsigned int wake; + + dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); + + for_each_set_bit(wake, &status, 32) { + irq_hw_number_t hwirq = wake + 32 * index; + struct irq_desc *desc; + unsigned int irq; + + irq = irq_find_mapping(pmc->domain, hwirq); + + desc = irq_to_desc(irq); + if (!desc || !desc->action || !desc->action->name) { + dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); + continue; + } + + dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); + generic_handle_irq(irq); + } +} + +static void tegra186_pmc_wake_syscore_resume(void) +{ + u32 status, mask; + unsigned int i; + + for (i = 0; i < pmc->soc->max_wake_vectors; i++) { + mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); + status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; + + tegra186_pmc_process_wake_events(pmc, i, status); + } +} + +static int tegra186_pmc_wake_syscore_suspend(void) +{ + wke_read_sw_wake_status(pmc); + + /* flip the wakeup trigger for dual-edge triggered pads + * which are currently asserting as wakeups + */ + bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, + pmc->wake_sw_status_map, pmc->soc->max_wake_events); + bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, + pmc->wake_type_level_map, pmc->soc->max_wake_events); + + /* Clear PMC Wake Status registers while going to suspend */ + wke_clear_wake_status(pmc); + wke_write_wake_levels(pmc); + + return 0; +} + #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) static int tegra_pmc_suspend(struct device *dev) { @@ -3050,10 +3241,6 @@ static const char * const tegra20_powergates[] = { static const struct tegra_pmc_regs tegra20_pmc_regs = { .scratch0 = 0x50, - .dpd_req = 0x1b8, - .dpd_status = 0x1bc, - .dpd2_req = 0x1c0, - .dpd2_status = 0x1c4, .rst_status = 0x1b4, .rst_source_shift = 0x0, .rst_source_mask = 0x7, @@ -3297,59 +3484,86 @@ static const u8 tegra124_cpu_powergates[] = { TEGRA_POWERGATE_CPU3, }; -#define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ - ((struct tegra_io_pad_soc) { \ - .id = (_id), \ - .dpd = (_dpd), \ - .voltage = (_voltage), \ - .name = (_name), \ +#define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \ + ((struct tegra_io_pad_soc) { \ + .id = (_id), \ + .dpd = (_dpd), \ + .request = (_request), \ + .status = (_status), \ + .voltage = (_voltage), \ + .name = (_name), \ }) -#define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ - ((struct pinctrl_pin_desc) { \ - .number = (_id), \ - .name = (_name) \ +#define TEGRA_IO_PIN_DESC(_id, _name) \ + ((struct pinctrl_pin_desc) { \ + .number = (_id), \ + .name = (_name), \ }) -#define TEGRA124_IO_PAD_TABLE(_pad) \ - /* .id .dpd .voltage .name */ \ - _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ - _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ - _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ - _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ - _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ - _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ - _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ - _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ - _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ - _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ - _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ - _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ - _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ - _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ - _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ - _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ - _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ - _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ - _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ - _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ - _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ - _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ - _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ - _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ - _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ - _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ - _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ - _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ - _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ - _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") - static const struct tegra_io_pad_soc tegra124_io_pads[] = { - TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"), + TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"), + TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), + TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"), }; static const struct pinctrl_pin_desc tegra124_pin_descs[] = { - TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"), }; static const struct tegra_pmc_soc tegra124_pmc_soc = { @@ -3415,53 +3629,86 @@ static const u8 tegra210_cpu_powergates[] = { TEGRA_POWERGATE_CPU3, }; -#define TEGRA210_IO_PAD_TABLE(_pad) \ - /* .id .dpd .voltage .name */ \ - _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ - _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ - _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ - _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ - _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ - _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ - _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ - _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ - _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ - _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ - _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ - _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ - _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ - _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ - _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ - _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ - _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ - _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ - _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ - _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ - _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ - _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ - _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ - _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ - _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ - _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ - _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ - _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ - _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ - _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ - _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ - _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ - _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ - _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ - _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ - _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ - _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ - _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") - static const struct tegra_io_pad_soc tegra210_io_pads[] = { - TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), + TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"), + TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), + TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"), }; static const struct pinctrl_pin_desc tegra210_pin_descs[] = { - TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), }; static const char * const tegra210_reset_sources[] = { @@ -3511,61 +3758,90 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .has_usb_sleepwalk = true, }; -#define TEGRA186_IO_PAD_TABLE(_pad) \ - /* .id .dpd .voltage .name */ \ - _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ - _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ - _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ - _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ - _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ - _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ - _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ - _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ - _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ - _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ - _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ - _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ - _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ - _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ - _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ - _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ - _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ - _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ - _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ - _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ - _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ - _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ - _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ - _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ - _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ - _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ - _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ - _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ - _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ - _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ - _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ - _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ - _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ - _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ - _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ - _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ - _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ - _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") - static const struct tegra_io_pad_soc tegra186_io_pads[] = { - TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), }; static const struct pinctrl_pin_desc tegra186_pin_descs[] = { - TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), }; static const struct tegra_pmc_regs tegra186_pmc_regs = { .scratch0 = 0x2000, - .dpd_req = 0x74, - .dpd_status = 0x78, - .dpd2_req = 0x7c, - .dpd2_status = 0x80, .rst_status = 0x70, .rst_source_shift = 0x2, .rst_source_mask = 0x3c, @@ -3573,6 +3849,14 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = { .rst_level_mask = 0x3, }; +static void tegra186_pmc_init(struct tegra_pmc *pmc) +{ + pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; + pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; + + register_syscore_ops(&pmc->syscore); +} + static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, struct device_node *np, bool invert) @@ -3652,7 +3936,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), .pin_descs = tegra186_pin_descs, .regs = &tegra186_pmc_regs, - .init = NULL, + .init = tegra186_pmc_init, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, .irq_set_wake = tegra186_pmc_irq_set_wake, .irq_set_type = tegra186_pmc_irq_set_type, @@ -3662,78 +3946,120 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), .num_wake_events = ARRAY_SIZE(tegra186_wake_events), .wake_events = tegra186_wake_events, + .max_wake_events = 96, + .max_wake_vectors = 3, .pmc_clks_data = NULL, .num_pmc_clks = 0, .has_blink_output = false, .has_usb_sleepwalk = false, }; -#define TEGRA194_IO_PAD_TABLE(_pad) \ - /* .id .dpd .voltage .name */ \ - _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ - _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ - _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ - _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ - _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ - _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ - _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ - _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \ - _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \ - _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \ - _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \ - _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \ - _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ - _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \ - _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \ - _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ - _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \ - _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \ - _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \ - _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \ - _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \ - _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \ - _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \ - _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ - _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \ - _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \ - _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ - _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ - _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ - _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \ - _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \ - _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \ - _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ - _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \ - _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ - _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ - _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ - _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ - _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ - _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ - _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ - _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \ - _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \ - _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ - _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ - _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ - _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ - _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ - _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") - static const struct tegra_io_pad_soc tegra194_io_pads[] = { - TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD) + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), + TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"), + TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), }; static const struct pinctrl_pin_desc tegra194_pin_descs[] = { - TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), }; static const struct tegra_pmc_regs tegra194_pmc_regs = { .scratch0 = 0x2000, - .dpd_req = 0x74, - .dpd_status = 0x78, - .dpd2_req = 0x7c, - .dpd2_status = 0x80, .rst_status = 0x70, .rst_source_shift = 0x2, .rst_source_mask = 0x7c, @@ -3794,7 +4120,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), .pin_descs = tegra194_pin_descs, .regs = &tegra194_pmc_regs, - .init = NULL, + .init = tegra186_pmc_init, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, .irq_set_wake = tegra186_pmc_irq_set_wake, .irq_set_type = tegra186_pmc_irq_set_type, @@ -3804,18 +4130,52 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), .num_wake_events = ARRAY_SIZE(tegra194_wake_events), .wake_events = tegra194_wake_events, + .max_wake_events = 96, + .max_wake_vectors = 3, .pmc_clks_data = NULL, .num_pmc_clks = 0, .has_blink_output = false, .has_usb_sleepwalk = false, }; +static const struct tegra_io_pad_soc tegra234_io_pads[] = { + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"), + TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"), +}; + +static const struct pinctrl_pin_desc tegra234_pin_descs[] = { + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), +}; + static const struct tegra_pmc_regs tegra234_pmc_regs = { .scratch0 = 0x2000, - .dpd_req = 0, - .dpd_status = 0, - .dpd2_req = 0, - .dpd2_status = 0, .rst_status = 0x70, .rst_source_shift = 0x2, .rst_source_mask = 0xfc, @@ -3880,12 +4240,12 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = { .needs_mbist_war = false, .has_impl_33v_pwr = true, .maybe_tz_only = false, - .num_io_pads = 0, - .io_pads = NULL, - .num_pin_descs = 0, - .pin_descs = NULL, + .num_io_pads = ARRAY_SIZE(tegra234_io_pads), + .io_pads = tegra234_io_pads, + .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs), + .pin_descs = tegra234_pin_descs, .regs = &tegra234_pmc_regs, - .init = NULL, + .init = tegra186_pmc_init, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, .irq_set_wake = tegra186_pmc_irq_set_wake, .irq_set_type = tegra186_pmc_irq_set_type, @@ -3895,6 +4255,8 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = { .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), .num_wake_events = ARRAY_SIZE(tegra234_wake_events), .wake_events = tegra234_wake_events, + .max_wake_events = 96, + .max_wake_vectors = 3, .pmc_clks_data = NULL, .num_pmc_clks = 0, .has_blink_output = false, diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 7e2fb1c16af1..e009d9589af4 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -63,7 +63,7 @@ config TI_SCI_PM_DOMAINS rootfs may be available. config TI_K3_RINGACC - bool "K3 Ring accelerator Sub System" + tristate "K3 Ring accelerator Sub System" depends on ARCH_K3 || COMPILE_TEST depends on TI_SCI_INTA_IRQCHIP help diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index f7bf18b8229a..e01e4d815230 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -7,7 +7,7 @@ #include <linux/dma-mapping.h> #include <linux/io.h> -#include <linux/init.h> +#include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/platform_device.h> @@ -336,6 +336,9 @@ struct k3_ring *k3_ringacc_request_ring(struct k3_ringacc *ringacc, mutex_lock(&ringacc->req_lock); + if (!try_module_get(ringacc->dev->driver->owner)) + goto err_module_get; + if (id == K3_RINGACC_RING_ID_ANY) { /* Request for any general purpose ring */ struct ti_sci_resource_desc *gp_rings = @@ -380,6 +383,9 @@ out: return &ringacc->rings[id]; error: + module_put(ringacc->dev->driver->owner); + +err_module_get: mutex_unlock(&ringacc->req_lock); return NULL; } @@ -616,6 +622,8 @@ int k3_ringacc_ring_free(struct k3_ring *ring) no_init: clear_bit(ring->ring_id, ringacc->rings_inuse); + module_put(ringacc->dev->driver->owner); + out: mutex_unlock(&ringacc->req_lock); return 0; @@ -1450,6 +1458,7 @@ static const struct of_device_id k3_ringacc_of_match[] = { { .compatible = "ti,am654-navss-ringacc", .data = &k3_ringacc_data, }, {}, }; +MODULE_DEVICE_TABLE(of, k3_ringacc_of_match); struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev, struct k3_ringacc_init_data *data) @@ -1544,12 +1553,27 @@ static int k3_ringacc_probe(struct platform_device *pdev) return 0; } +static int k3_ringacc_remove(struct platform_device *pdev) +{ + struct k3_ringacc *ringacc = dev_get_drvdata(&pdev->dev); + + mutex_lock(&k3_ringacc_list_lock); + list_del(&ringacc->list); + mutex_unlock(&k3_ringacc_list_lock); + return 0; +} + static struct platform_driver k3_ringacc_driver = { .probe = k3_ringacc_probe, + .remove = k3_ringacc_remove, .driver = { .name = "k3-ringacc", .of_match_table = k3_ringacc_of_match, .suppress_bind_attrs = true, }, }; -builtin_platform_driver(k3_ringacc_driver); +module_platform_driver(k3_ringacc_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("TI Ringacc driver for K3 SOCs"); +MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index 91f441ee6175..d15764e19d96 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -43,6 +43,7 @@ static const struct k3_soc_id { { 0xBB38, "AM64X" }, { 0xBB75, "J721S2"}, { 0xBB7E, "AM62X" }, + { 0xBB8D, "AM62AX" }, }; static int diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c index 92af7d1b6f5b..8fb76908be70 100644 --- a/drivers/soc/ti/knav_qmss_queue.c +++ b/drivers/soc/ti/knav_qmss_queue.c @@ -67,7 +67,7 @@ static DEFINE_MUTEX(knav_dev_lock); * Newest followed by older ones. Search is done from start of the array * until a firmware file is found. */ -const char *knav_acc_firmwares[] = {"ks2_qmss_pdsp_acc48.bin"}; +static const char * const knav_acc_firmwares[] = {"ks2_qmss_pdsp_acc48.bin"}; static bool device_ready; bool knav_qmss_device_ready(void) @@ -1785,6 +1785,7 @@ static int knav_queue_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); ret = pm_runtime_resume_and_get(&pdev->dev); if (ret < 0) { + pm_runtime_disable(&pdev->dev); dev_err(dev, "Failed to enable QMSS\n"); return ret; } diff --git a/drivers/soc/ti/smartreflex.c b/drivers/soc/ti/smartreflex.c index ad2bb72e640c..6a389a6444f3 100644 --- a/drivers/soc/ti/smartreflex.c +++ b/drivers/soc/ti/smartreflex.c @@ -932,6 +932,7 @@ static int omap_sr_probe(struct platform_device *pdev) err_debugfs: debugfs_remove_recursive(sr_info->dbg_dir); err_list_del: + pm_runtime_disable(&pdev->dev); list_del(&sr_info->node); clk_unprepare(sr_info->fck); diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index daf07737c4fd..2a258bd3b6b5 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -188,7 +188,7 @@ void optee_remove_common(struct optee *optee) static int smc_abi_rc; static int ffa_abi_rc; -static int optee_core_init(void) +static int __init optee_core_init(void) { /* * The kernel may have crashed at the same time that all available @@ -210,7 +210,7 @@ static int optee_core_init(void) } module_init(optee_core_init); -static void optee_core_exit(void) +static void __exit optee_core_exit(void) { if (!smc_abi_rc) optee_smc_abi_unregister(); diff --git a/drivers/thermal/tegra/tegra-bpmp-thermal.c b/drivers/thermal/tegra/tegra-bpmp-thermal.c index eb84f0b9dc7c..0b7a1a1948cb 100644 --- a/drivers/thermal/tegra/tegra-bpmp-thermal.c +++ b/drivers/thermal/tegra/tegra-bpmp-thermal.c @@ -106,21 +106,22 @@ static void tz_device_update_work_fn(struct work_struct *work) static void bpmp_mrq_thermal(unsigned int mrq, struct tegra_bpmp_channel *ch, void *data) { - struct mrq_thermal_bpmp_to_host_request *req; + struct mrq_thermal_bpmp_to_host_request req; struct tegra_bpmp_thermal *tegra = data; + size_t offset; int i; - req = (struct mrq_thermal_bpmp_to_host_request *)ch->ib->data; + offset = offsetof(struct tegra_bpmp_mb_data, data); + iosys_map_memcpy_from(&req, &ch->ib, offset, sizeof(req)); - if (req->type != CMD_THERMAL_HOST_TRIP_REACHED) { - dev_err(tegra->dev, "%s: invalid request type: %d\n", - __func__, req->type); + if (req.type != CMD_THERMAL_HOST_TRIP_REACHED) { + dev_err(tegra->dev, "%s: invalid request type: %d\n", __func__, req.type); tegra_bpmp_mrq_return(ch, -EINVAL, NULL, 0); return; } for (i = 0; i < tegra->num_zones; ++i) { - if (tegra->zones[i]->idx != req->host_trip_reached.zone) + if (tegra->zones[i]->idx != req.host_trip_reached.zone) continue; schedule_work(&tegra->zones[i]->tz_device_update_work); @@ -129,7 +130,7 @@ static void bpmp_mrq_thermal(unsigned int mrq, struct tegra_bpmp_channel *ch, } dev_err(tegra->dev, "%s: invalid thermal zone: %d\n", __func__, - req->host_trip_reached.zone); + req.host_trip_reached.zone); tegra_bpmp_mrq_return(ch, -EINVAL, NULL, 0); } diff --git a/drivers/usb/host/fhci-hcd.c b/drivers/usb/host/fhci-hcd.c index 95a44462bed0..1f666804fa91 100644 --- a/drivers/usb/host/fhci-hcd.c +++ b/drivers/usb/host/fhci-hcd.c @@ -651,7 +651,7 @@ static int of_fhci_probe(struct platform_device *ofdev) } for (j = 0; j < NUM_PINS; j++) { - fhci->pins[j] = qe_pin_request(node, j); + fhci->pins[j] = qe_pin_request(dev, j); if (IS_ERR(fhci->pins[j])) { ret = PTR_ERR(fhci->pins[j]); dev_err(dev, "can't get pin %d: %d\n", j, ret); diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h new file mode 100644 index 000000000000..f7aef3f310d7 --- /dev/null +++ b/include/dt-bindings/arm/qcom,ids.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> based on previous work of Kumar Gala. + */ +#ifndef _DT_BINDINGS_ARM_QCOM_IDS_H +#define _DT_BINDINGS_ARM_QCOM_IDS_H + +/* + * The MSM chipset and hardware revision used by Qualcomm bootloaders, DTS for + * older chipsets (qcom,msm-id) and in socinfo driver: + */ +#define QCOM_ID_MSM8960 87 +#define QCOM_ID_APQ8064 109 +#define QCOM_ID_MSM8660A 122 +#define QCOM_ID_MSM8260A 123 +#define QCOM_ID_APQ8060A 124 +#define QCOM_ID_MSM8974 126 +#define QCOM_ID_MPQ8064 130 +#define QCOM_ID_MSM8960AB 138 +#define QCOM_ID_APQ8060AB 139 +#define QCOM_ID_MSM8260AB 140 +#define QCOM_ID_MSM8660AB 141 +#define QCOM_ID_MSM8626 145 +#define QCOM_ID_MSM8610 147 +#define QCOM_ID_APQ8064AB 153 +#define QCOM_ID_MSM8226 158 +#define QCOM_ID_MSM8526 159 +#define QCOM_ID_MSM8110 161 +#define QCOM_ID_MSM8210 162 +#define QCOM_ID_MSM8810 163 +#define QCOM_ID_MSM8212 164 +#define QCOM_ID_MSM8612 165 +#define QCOM_ID_MSM8112 166 +#define QCOM_ID_MSM8225Q 168 +#define QCOM_ID_MSM8625Q 169 +#define QCOM_ID_MSM8125Q 170 +#define QCOM_ID_APQ8064AA 172 +#define QCOM_ID_APQ8084 178 +#define QCOM_ID_APQ8074 184 +#define QCOM_ID_MSM8274 185 +#define QCOM_ID_MSM8674 186 +#define QCOM_ID_MSM8974PRO_AC 194 +#define QCOM_ID_MSM8126 198 +#define QCOM_ID_APQ8026 199 +#define QCOM_ID_MSM8926 200 +#define QCOM_ID_MSM8326 205 +#define QCOM_ID_MSM8916 206 +#define QCOM_ID_MSM8994 207 +#define QCOM_ID_APQ8074PRO_AA 208 +#define QCOM_ID_APQ8074PRO_AB 209 +#define QCOM_ID_APQ8074PRO_AC 210 +#define QCOM_ID_MSM8274PRO_AA 211 +#define QCOM_ID_MSM8274PRO_AB 212 +#define QCOM_ID_MSM8274PRO_AC 213 +#define QCOM_ID_MSM8674PRO_AA 214 +#define QCOM_ID_MSM8674PRO_AB 215 +#define QCOM_ID_MSM8674PRO_AC 216 +#define QCOM_ID_MSM8974PRO_AA 217 +#define QCOM_ID_MSM8974PRO_AB 218 +#define QCOM_ID_APQ8028 219 +#define QCOM_ID_MSM8128 220 +#define QCOM_ID_MSM8228 221 +#define QCOM_ID_MSM8528 222 +#define QCOM_ID_MSM8628 223 +#define QCOM_ID_MSM8928 224 +#define QCOM_ID_MSM8510 225 +#define QCOM_ID_MSM8512 226 +#define QCOM_ID_MSM8936 233 +#define QCOM_ID_MSM8939 239 +#define QCOM_ID_APQ8036 240 +#define QCOM_ID_APQ8039 241 +#define QCOM_ID_MSM8996 246 +#define QCOM_ID_APQ8016 247 +#define QCOM_ID_MSM8216 248 +#define QCOM_ID_MSM8116 249 +#define QCOM_ID_MSM8616 250 +#define QCOM_ID_MSM8992 251 +#define QCOM_ID_APQ8094 253 +#define QCOM_ID_MSM8956 266 +#define QCOM_ID_MSM8976 278 +#define QCOM_ID_MDM9607 290 +#define QCOM_ID_APQ8096 291 +#define QCOM_ID_MSM8998 292 +#define QCOM_ID_MSM8953 293 +#define QCOM_ID_MDM8207 296 +#define QCOM_ID_MDM9207 297 +#define QCOM_ID_MDM9307 298 +#define QCOM_ID_MDM9628 299 +#define QCOM_ID_APQ8053 304 +#define QCOM_ID_MSM8996SG 305 +#define QCOM_ID_MSM8996AU 310 +#define QCOM_ID_APQ8096AU 311 +#define QCOM_ID_APQ8096SG 312 +#define QCOM_ID_SDM660 317 +#define QCOM_ID_SDM630 318 +#define QCOM_ID_APQ8098 319 +#define QCOM_ID_SDM845 321 +#define QCOM_ID_MDM9206 322 +#define QCOM_ID_IPQ8074 323 +#define QCOM_ID_SDA660 324 +#define QCOM_ID_SDM658 325 +#define QCOM_ID_SDA658 326 +#define QCOM_ID_SDA630 327 +#define QCOM_ID_SDM450 338 +#define QCOM_ID_SM8150 339 +#define QCOM_ID_SDA845 341 +#define QCOM_ID_IPQ8072 342 +#define QCOM_ID_IPQ8076 343 +#define QCOM_ID_IPQ8078 344 +#define QCOM_ID_SDM636 345 +#define QCOM_ID_SDA636 346 +#define QCOM_ID_SDM632 349 +#define QCOM_ID_SDA632 350 +#define QCOM_ID_SDA450 351 +#define QCOM_ID_SM8250 356 +#define QCOM_ID_SA8155 362 +#define QCOM_ID_IPQ8070 375 +#define QCOM_ID_IPQ8071 376 +#define QCOM_ID_IPQ8072A 389 +#define QCOM_ID_IPQ8074A 390 +#define QCOM_ID_IPQ8076A 391 +#define QCOM_ID_IPQ8078A 392 +#define QCOM_ID_SM6125 394 +#define QCOM_ID_IPQ8070A 395 +#define QCOM_ID_IPQ8071A 396 +#define QCOM_ID_IPQ6018 402 +#define QCOM_ID_IPQ6028 403 +#define QCOM_ID_SM4250 417 +#define QCOM_ID_IPQ6000 421 +#define QCOM_ID_IPQ6010 422 +#define QCOM_ID_SC7180 425 +#define QCOM_ID_SM6350 434 +#define QCOM_ID_SM8350 439 +#define QCOM_ID_SM6115 444 +#define QCOM_ID_SC8280XP 449 +#define QCOM_ID_IPQ6005 453 +#define QCOM_ID_QRB5165 455 +#define QCOM_ID_SM8450 457 +#define QCOM_ID_SM7225 459 +#define QCOM_ID_SA8295P 460 +#define QCOM_ID_SA8540P 461 +#define QCOM_ID_QCM4290 469 +#define QCOM_ID_QCS4290 470 +#define QCOM_ID_SM8450_2 480 +#define QCOM_ID_SM8450_3 482 +#define QCOM_ID_SC7280 487 +#define QCOM_ID_SC7180P 495 +#define QCOM_ID_SM6375 507 +#define QCOM_ID_SM8550 519 +#define QCOM_ID_QRU1000 539 +#define QCOM_ID_QDU1000 545 +#define QCOM_ID_QDU1010 587 +#define QCOM_ID_QRU1032 588 +#define QCOM_ID_QRU1052 589 +#define QCOM_ID_QRU1062 590 + +/* + * The board type and revision information, used by Qualcomm bootloaders and + * DTS for older chipsets (qcom,board-id): + */ +#define QCOM_BOARD_ID(a, major, minor) \ + (((major & 0xff) << 16) | ((minor & 0xff) << 8) | QCOM_BOARD_ID_##a) + +#define QCOM_BOARD_ID_MTP 8 +#define QCOM_BOARD_ID_DRAGONBOARD 10 +#define QCOM_BOARD_ID_SBC 24 + +#endif /* _DT_BINDINGS_ARM_QCOM_IDS_H */ diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 173364a93381..c360455d02ee 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -9,6 +9,12 @@ * @defgroup bpmp_clock_ids Clock ID's * @{ */ +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */ +#define TEGRA234_CLK_ACTMON 1U +/** @brief output of gate CLK_ENB_ADSP */ +#define TEGRA234_CLK_ADSP 2U +/** @brief output of gate CLK_ENB_ADSPNEON */ +#define TEGRA234_CLK_ADSPNEON 3U /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ #define TEGRA234_CLK_AHUB 4U /** @brief output of gate CLK_ENB_APB2APE */ @@ -17,6 +23,18 @@ #define TEGRA234_CLK_APE 6U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ #define TEGRA234_CLK_AUD_MCLK 7U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ +#define TEGRA234_CLK_AXI_CBB 8U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ +#define TEGRA234_CLK_CAN1 9U +/** @brief output of gate CLK_ENB_CAN1_HOST */ +#define TEGRA234_CLK_CAN1_HOST 10U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ +#define TEGRA234_CLK_CAN2 11U +/** @brief output of gate CLK_ENB_CAN2_HOST */ +#define TEGRA234_CLK_CAN2_HOST 12U +/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ +#define TEGRA234_CLK_CLK_M 14U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ #define TEGRA234_CLK_DMIC1 15U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ @@ -25,6 +43,28 @@ #define TEGRA234_CLK_DMIC3 17U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ #define TEGRA234_CLK_DMIC4 18U +/** @brief output of gate CLK_ENB_DPAUX */ +#define TEGRA234_CLK_DPAUX 19U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */ +#define TEGRA234_CLK_NVJPG1 20U +/** + * @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY + * divided by the divider controlled by ACLK_CLK_DIVISOR in + * CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER + */ +#define TEGRA234_CLK_ACLK 21U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */ +#define TEGRA234_CLK_MSS_ENCRYPT 22U +/** @brief clock recovered from EAVB input */ +#define TEGRA234_CLK_EQOS_RX_INPUT 23U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */ +#define TEGRA234_CLK_AON_APB 25U +/** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */ +#define TEGRA234_CLK_AON_NIC 26U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */ +#define TEGRA234_CLK_AON_CPU_NIC 27U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ +#define TEGRA234_CLK_PLLA1 28U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ #define TEGRA234_CLK_DSPK1 29U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ @@ -38,10 +78,33 @@ * throughput and memory controller power. */ #define TEGRA234_CLK_EMC 31U -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ -#define TEGRA234_CLK_HOST1X 46U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */ +#define TEGRA234_CLK_EQOS_AXI 32U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */ +#define TEGRA234_CLK_EQOS_PTP_REF 33U +/** @brief output of gate CLK_ENB_EQOS_RX */ +#define TEGRA234_CLK_EQOS_RX 34U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */ +#define TEGRA234_CLK_EQOS_TX 35U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ +#define TEGRA234_CLK_EXTPERIPH1 36U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ +#define TEGRA234_CLK_EXTPERIPH2 37U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ +#define TEGRA234_CLK_EXTPERIPH3 38U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ +#define TEGRA234_CLK_EXTPERIPH4 39U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U +/** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */ +#define TEGRA234_CLK_GPC0CLK 41U +/** @brief TODO */ +#define TEGRA234_CLK_GPU_PWR 42U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +#define TEGRA234_CLK_HOST1X 46U +/** @brief xusb_hs_hsicp_clk */ +#define TEGRA234_CLK_XUSB_HS_HSICP 47U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ #define TEGRA234_CLK_I2C1 48U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ @@ -82,10 +145,66 @@ #define TEGRA234_CLK_I2S6 66U /** @brief clock recovered from I2S6 input */ #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ +#define TEGRA234_CLK_ISP 69U +/** @brief Monitored branch of EQOS_RX clock */ +#define TEGRA234_CLK_EQOS_RX_M 70U +/** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */ +#define TEGRA234_CLK_MAUD 71U +/** @brief output of gate CLK_ENB_MIPI_CAL */ +#define TEGRA234_CLK_MIPI_CAL 72U +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ +#define TEGRA234_CLK_MPHY_CORE_PLL_FIXED 73U +/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ +#define TEGRA234_CLK_MPHY_L0_RX_ANA 74U +/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ +#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT 75U +/** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */ +#define TEGRA234_CLK_MPHY_L0_RX_SYMB 76U +/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ +#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT 77U +/** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */ +#define TEGRA234_CLK_MPHY_L0_TX_SYMB 78U +/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ +#define TEGRA234_CLK_MPHY_L1_RX_ANA 79U +/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ +#define TEGRA234_CLK_MPHY_TX_1MHZ_REF 80U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ +#define TEGRA234_CLK_NVCSI 81U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ +#define TEGRA234_CLK_NVCSILP 82U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ +#define TEGRA234_CLK_NVDEC 83U +/** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITCH_DIVIDER switch divider output (hubclk) */ +#define TEGRA234_CLK_HUB 84U +/** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_DIVIDER switch divider output (dispclk) */ +#define TEGRA234_CLK_DISP 85U +/** @brief RG_CLK_CTRL__0_DIV divider output (nvdisplay_p0_clk) */ +#define TEGRA234_CLK_NVDISPLAY_P0 86U +/** @brief RG_CLK_CTRL__1_DIV divider output (nvdisplay_p1_clk) */ +#define TEGRA234_CLK_NVDISPLAY_P1 87U +/** @brief DSC_CLK (DISPCLK ÷ 3) */ +#define TEGRA234_CLK_DSC 88U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ +#define TEGRA234_CLK_NVENC 89U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ +#define TEGRA234_CLK_NVJPG 90U +/** @brief input from Tegra's XTAL_IN */ +#define TEGRA234_CLK_OSC 91U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH switch divider output */ +#define TEGRA234_CLK_AON_TOUCH 92U /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ #define TEGRA234_CLK_PLLA 93U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ +#define TEGRA234_CLK_PLLAON 94U +/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ +#define TEGRA234_CLK_PLLE 100U +/** @brief PLLP vco output */ +#define TEGRA234_CLK_PLLP 101U /** @brief PLLP clk output */ #define TEGRA234_CLK_PLLP_OUT0 102U +/** Fixed frequency 960MHz PLL for USB and EAVB */ +#define TEGRA234_CLK_UTMIP_PLL 103U /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ #define TEGRA234_CLK_PLLA_OUT0 104U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ @@ -104,8 +223,50 @@ #define TEGRA234_CLK_PWM7 111U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ #define TEGRA234_CLK_PWM8 112U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC output */ +#define TEGRA234_CLK_RCE_CPU_NIC 113U +/** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE divider output */ +#define TEGRA234_CLK_RCE_NIC 114U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW switch divider output */ +#define TEGRA234_CLK_AON_I2C_SLOW 117U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ +#define TEGRA234_CLK_SCE_CPU_NIC 118U +/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ +#define TEGRA234_CLK_SCE_NIC 119U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ +#define TEGRA234_CLK_SDMMC1 120U +/** @brief Logical clk for setting the UPHY PLL3 rate */ +#define TEGRA234_CLK_UPHY_PLL3 121U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ #define TEGRA234_CLK_SDMMC4 123U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */ +#define TEGRA234_CLK_SE 124U +/** @brief VPLL select for sor0_ref clk driven by disp_2clk_sor0_head_sel signal */ +#define TEGRA234_CLK_SOR0_PLL_REF 125U +/** @brief Output of mux controlled by disp_2clk_sor0_pll_ref_clk_safe signal (sor0_ref_clk) */ +#define TEGRA234_CLK_SOR0_REF 126U +/** @brief VPLL select for sor1_ref clk driven by disp_2clk_sor0_head_sel signal */ +#define TEGRA234_CLK_SOR1_PLL_REF 127U +/** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider output */ +#define TEGRA234_CLK_PRE_SOR0_REF 128U +/** @brief Output of mux controlled by disp_2clk_sor1_pll_ref_clk_safe signal (sor1_ref_clk) */ +#define TEGRA234_CLK_SOR1_REF 129U +/** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider output */ +#define TEGRA234_CLK_PRE_SOR1_REF 130U +/** @brief output of gate CLK_ENB_SOR_SAFE */ +#define TEGRA234_CLK_SOR_SAFE 131U +/** @brief SOR_CLK_CTRL__0_DIV divider output */ +#define TEGRA234_CLK_SOR0_DIV 132U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ +#define TEGRA234_CLK_DMIC5 134U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ +#define TEGRA234_CLK_SPI1 135U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ +#define TEGRA234_CLK_SPI2 136U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI3 */ +#define TEGRA234_CLK_SPI3 137U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ +#define TEGRA234_CLK_I2C_SLOW 138U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ #define TEGRA234_CLK_SYNC_DMIC1 139U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ @@ -130,28 +291,132 @@ #define TEGRA234_CLK_SYNC_I2S5 149U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ #define TEGRA234_CLK_SYNC_I2S6 150U +/** @brief controls MPHY_FORCE_LS_MODE upon enable & disable */ +#define TEGRA234_CLK_MPHY_FORCE_LS_MODE 151U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH0 */ +#define TEGRA234_CLK_TACH0 152U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ +#define TEGRA234_CLK_TSEC 153U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */ +#define TEGRA234_CLK_TSEC_PKA 154U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ #define TEGRA234_CLK_UARTA 155U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ +#define TEGRA234_CLK_UARTB 156U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ +#define TEGRA234_CLK_UARTC 157U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ +#define TEGRA234_CLK_UARTD 158U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ +#define TEGRA234_CLK_UARTE 159U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ +#define TEGRA234_CLK_UARTF 160U /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ #define TEGRA234_CLK_PEX1_C6_CORE 161U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ +#define TEGRA234_CLK_UART_FST_MIPI_CAL 162U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ +#define TEGRA234_CLK_UFSDEV_REF 163U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ +#define TEGRA234_CLK_UFSHC 164U +/** @brief output of gate CLK_ENB_USB2_TRK */ +#define TEGRA234_CLK_USB2_TRK 165U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ +#define TEGRA234_CLK_VI 166U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ -#define TEGRA234_CLK_VIC 167U +#define TEGRA234_CLK_VIC 167U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE switch divider output */ +#define TEGRA234_CLK_CSITE 168U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST switch divider output */ +#define TEGRA234_CLK_IST 169U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_IST_JTAG_REG_CLK_SEL */ +#define TEGRA234_CLK_JTAG_INTFC_PRE_CG 170U /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ #define TEGRA234_CLK_PEX2_C7_CORE 171U /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ #define TEGRA234_CLK_PEX2_C8_CORE 172U /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ #define TEGRA234_CLK_PEX2_C9_CORE 173U +/** @brief dla0_falcon_clk */ +#define TEGRA234_CLK_DLA0_FALCON 174U +/** @brief dla0_core_clk */ +#define TEGRA234_CLK_DLA0_CORE 175U +/** @brief dla1_falcon_clk */ +#define TEGRA234_CLK_DLA1_FALCON 176U +/** @brief dla1_core_clk */ +#define TEGRA234_CLK_DLA1_CORE 177U +/** @brief Output of mux controlled by disp_2clk_sor0_clk_safe signal (sor0_clk) */ +#define TEGRA234_CLK_SOR0 178U +/** @brief Output of mux controlled by disp_2clk_sor1_clk_safe signal (sor1_clk) */ +#define TEGRA234_CLK_SOR1 179U +/** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */ +#define TEGRA234_CLK_SOR_PAD_INPUT 180U +/** @brief Output of mux controlled by disp_2clk_h0_dsi_sel signal in sf0_clk path */ +#define TEGRA234_CLK_PRE_SF0 181U +/** @brief Output of mux controlled by disp_2clk_sf0_clk_safe signal (sf0_clk) */ +#define TEGRA234_CLK_SF0 182U +/** @brief Output of mux controlled by disp_2clk_sf1_clk_safe signal (sf1_clk) */ +#define TEGRA234_CLK_SF1 183U +/** @brief CLKOUT_AB output from DSI BRICK A (dsi_clkout_ab) */ +#define TEGRA234_CLK_DSI_PAD_INPUT 184U /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ #define TEGRA234_CLK_PEX2_C10_CORE 187U -/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI switch divider output (uarti_r_clk) */ +#define TEGRA234_CLK_UARTI 188U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ switch divider output (uartj_r_clk) */ +#define TEGRA234_CLK_UARTJ 189U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */ +#define TEGRA234_CLK_UARTH 190U +/** @brief ungated version of fuse clk */ +#define TEGRA234_CLK_FUSE_SERIAL 191U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output (qspi0_2x_pm_clk) */ #define TEGRA234_CLK_QSPI0_2X_PM 192U -/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output (qspi1_2x_pm_clk) */ #define TEGRA234_CLK_QSPI1_2X_PM 193U -/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 (qspi0_pm_clk) */ #define TEGRA234_CLK_QSPI0_PM 194U -/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 (qspi1_pm_clk) */ #define TEGRA234_CLK_QSPI1_PM 195U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST switch divider output */ +#define TEGRA234_CLK_VI_CONST 196U +/** @brief NAFLL clock source for BPMP */ +#define TEGRA234_CLK_NAFLL_BPMP 197U +/** @brief NAFLL clock source for SCE */ +#define TEGRA234_CLK_NAFLL_SCE 198U +/** @brief NAFLL clock source for NVDEC */ +#define TEGRA234_CLK_NAFLL_NVDEC 199U +/** @brief NAFLL clock source for NVJPG */ +#define TEGRA234_CLK_NAFLL_NVJPG 200U +/** @brief NAFLL clock source for TSEC */ +#define TEGRA234_CLK_NAFLL_TSEC 201U +/** @brief NAFLL clock source for VI */ +#define TEGRA234_CLK_NAFLL_VI 203U +/** @brief NAFLL clock source for SE */ +#define TEGRA234_CLK_NAFLL_SE 204U +/** @brief NAFLL clock source for NVENC */ +#define TEGRA234_CLK_NAFLL_NVENC 205U +/** @brief NAFLL clock source for ISP */ +#define TEGRA234_CLK_NAFLL_ISP 206U +/** @brief NAFLL clock source for VIC */ +#define TEGRA234_CLK_NAFLL_VIC 207U +/** @brief NAFLL clock source for AXICBB */ +#define TEGRA234_CLK_NAFLL_AXICBB 209U +/** @brief NAFLL clock source for NVJPG1 */ +#define TEGRA234_CLK_NAFLL_NVJPG1 210U +/** @brief NAFLL clock source for PVA core */ +#define TEGRA234_CLK_NAFLL_PVA0_CORE 211U +/** @brief NAFLL clock source for PVA VPS */ +#define TEGRA234_CLK_NAFLL_PVA0_VPS 212U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0 switch divider output (dbgapb_clk) */ +#define TEGRA234_CLK_DBGAPB 213U +/** @brief NAFLL clock source for RCE */ +#define TEGRA234_CLK_NAFLL_RCE 214U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA switch divider output (la_r_clk) */ +#define TEGRA234_CLK_LA 215U +/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTD */ +#define TEGRA234_CLK_PLLP_OUT_JTAG 216U +/** @brief AXI_CBB branch sharing gate control with SDMMC4 */ +#define TEGRA234_CLK_SDMMC4_AXICIF 217U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ @@ -166,8 +431,42 @@ #define TEGRA234_CLK_PEX0_C4_CORE 224U /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ #define TEGRA234_CLK_PEX1_C5_CORE 225U +/** @brief Monitored branch of PEX0_C0_CORE clock */ +#define TEGRA234_CLK_PEX0_C0_CORE_M 229U +/** @brief Monitored branch of PEX0_C1_CORE clock */ +#define TEGRA234_CLK_PEX0_C1_CORE_M 230U +/** @brief Monitored branch of PEX0_C2_CORE clock */ +#define TEGRA234_CLK_PEX0_C2_CORE_M 231U +/** @brief Monitored branch of PEX0_C3_CORE clock */ +#define TEGRA234_CLK_PEX0_C3_CORE_M 232U +/** @brief Monitored branch of PEX0_C4_CORE clock */ +#define TEGRA234_CLK_PEX0_C4_CORE_M 233U +/** @brief Monitored branch of PEX1_C5_CORE clock */ +#define TEGRA234_CLK_PEX1_C5_CORE_M 234U +/** @brief Monitored branch of PEX1_C6_CORE clock */ +#define TEGRA234_CLK_PEX1_C6_CORE_M 235U +/** @brief output of GPU GPC1 clkGen (in 1x mode same rate as GPC1 MUX2 out) */ +#define TEGRA234_CLK_GPC1CLK 236U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ #define TEGRA234_CLK_PLLC4 237U +/** @brief PLLC4 VCO followed by DIV3 path */ +#define TEGRA234_CLK_PLLC4_OUT1 239U +/** @brief PLLC4 VCO followed by DIV5 path */ +#define TEGRA234_CLK_PLLC4_OUT2 240U +/** @brief output of the mux controlled by PLLC4_CLK_SEL */ +#define TEGRA234_CLK_PLLC4_MUXED 241U +/** @brief PLLC4 VCO followed by DIV2 path */ +#define TEGRA234_CLK_PLLC4_VCO_DIV2 242U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVHS_BASE */ +#define TEGRA234_CLK_PLLNVHS 243U +/** @brief Monitored branch of PEX2_C7_CORE clock */ +#define TEGRA234_CLK_PEX2_C7_CORE_M 244U +/** @brief Monitored branch of PEX2_C8_CORE clock */ +#define TEGRA234_CLK_PEX2_C8_CORE_M 245U +/** @brief Monitored branch of PEX2_C9_CORE clock */ +#define TEGRA234_CLK_PEX2_C9_CORE_M 246U +/** @brief Monitored branch of PEX2_C10_CORE clock */ +#define TEGRA234_CLK_PEX2_C10_CORE_M 247U /** @brief RX clock recovered from MGBE0 lane input */ #define TEGRA234_CLK_MGBE0_RX_INPUT 248U /** @brief RX clock recovered from MGBE1 lane input */ @@ -176,8 +475,185 @@ #define TEGRA234_CLK_MGBE2_RX_INPUT 250U /** @brief RX clock recovered from MGBE3 lane input */ #define TEGRA234_CLK_MGBE3_RX_INPUT 251U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP switch divider output */ +#define TEGRA234_CLK_PEX_SATA_USB_RX_BYP 254U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT switch divider output */ +#define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT 255U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT switch divider output */ +#define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT 256U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT switch divider output */ +#define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT 257U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT switch divider output */ +#define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT 258U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP switch divider output */ +#define TEGRA234_CLK_NVHS_RX_BYP_REF 263U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT switch divider output */ +#define TEGRA234_CLK_NVHS_PLL0_MGMT 264U +/** @brief xusb_core_dev_clk */ +#define TEGRA234_CLK_XUSB_CORE_DEV 265U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST switch divider output */ +#define TEGRA234_CLK_XUSB_CORE_MUX 266U +/** @brief xusb_core_host_clk */ +#define TEGRA234_CLK_XUSB_CORE_HOST 267U +/** @brief xusb_core_superspeed_clk */ +#define TEGRA234_CLK_XUSB_CORE_SS 268U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON switch divider output */ +#define TEGRA234_CLK_XUSB_FALCON 269U +/** @brief xusb_falcon_host_clk */ +#define TEGRA234_CLK_XUSB_FALCON_HOST 270U +/** @brief xusb_falcon_superspeed_clk */ +#define TEGRA234_CLK_XUSB_FALCON_SS 271U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS switch divider output */ +#define TEGRA234_CLK_XUSB_FS 272U +/** @brief xusb_fs_host_clk */ +#define TEGRA234_CLK_XUSB_FS_HOST 273U +/** @brief xusb_fs_dev_clk */ +#define TEGRA234_CLK_XUSB_FS_DEV 274U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS switch divider output */ +#define TEGRA234_CLK_XUSB_SS 275U +/** @brief xusb_ss_dev_clk */ +#define TEGRA234_CLK_XUSB_SS_DEV 276U +/** @brief xusb_ss_superspeed_clk */ +#define TEGRA234_CLK_XUSB_SS_SUPERSPEED 277U +/** @brief NAFLL clock source for CPU cluster 0 */ +#define TEGRA234_CLK_NAFLL_CLUSTER0 280U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER0_CORE 280U +/** @brief NAFLL clock source for CPU cluster 1 */ +#define TEGRA234_CLK_NAFLL_CLUSTER1 281U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER1_CORE 281U +/** @brief NAFLL clock source for CPU cluster 2 */ +#define TEGRA234_CLK_NAFLL_CLUSTER2 282U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER2_CORE 282U +/** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE divider output */ +#define TEGRA234_CLK_CAN1_CORE 284U +/** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE divider outputt */ +#define TEGRA234_CLK_CAN2_CORE 285U +/** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switch divider output */ +#define TEGRA234_CLK_PLLA1_OUT1 286U +/** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */ +#define TEGRA234_CLK_PLLNVHS_HPS 287U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE */ +#define TEGRA234_CLK_PLLREFE_VCOOUT 288U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief Fixed 48MHz clock divided down from utmipll */ +#define TEGRA234_CLK_UTMIPLL_CLKOUT48 291U +/** @brief Fixed 480MHz clock divided down from utmipll */ +#define TEGRA234_CLK_UTMIPLL_CLKOUT480 292U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ +#define TEGRA234_CLK_PLLNVCSI 294U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI switch divider output */ +#define TEGRA234_CLK_PVA0_CPU_AXI 295U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS switch divider output */ +#define TEGRA234_CLK_PVA0_VPS 297U +/** @brief DLA0_CORE_NAFLL */ +#define TEGRA234_CLK_NAFLL_DLA0_CORE 299U +/** @brief DLA0_FALCON_NAFLL */ +#define TEGRA234_CLK_NAFLL_DLA0_FALCON 300U +/** @brief DLA1_CORE_NAFLL */ +#define TEGRA234_CLK_NAFLL_DLA1_CORE 301U +/** @brief DLA1_FALCON_NAFLL */ +#define TEGRA234_CLK_NAFLL_DLA1_FALCON 302U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ +#define TEGRA234_CLK_AON_UART_FST_MIPI_CAL 303U +/** @brief GPU system clock */ +#define TEGRA234_CLK_GPUSYS 304U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 */ +#define TEGRA234_CLK_I2C5 305U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider free running clk */ +#define TEGRA234_CLK_FR_SE 306U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC switch divider output */ +#define TEGRA234_CLK_BPMP_CPU_NIC 307U +/** @brief output of gate CLK_ENB_BPMP_CPU */ +#define TEGRA234_CLK_BPMP_CPU 308U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC switch divider output */ +#define TEGRA234_CLK_TSC 309U +/** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */ +#define TEGRA234_CLK_EMCSA_MPLL 310U +/** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */ +#define TEGRA234_CLK_EMCSB_MPLL 311U +/** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */ +#define TEGRA234_CLK_EMCSC_MPLL 312U +/** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */ +#define TEGRA234_CLK_EMCSD_MPLL 313U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ +#define TEGRA234_CLK_PLLC 314U +/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ +#define TEGRA234_CLK_PLLC2 315U +/** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER skip divider output */ +#define TEGRA234_CLK_TSC_REF 317U +/** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */ +#define TEGRA234_CLK_FUSE_BURN 318U +/** @brief GBE PLL */ +#define TEGRA234_CLK_PLLGBE 319U +/** @brief GBE PLL hardware power sequencer */ +#define TEGRA234_CLK_PLLGBE_HPS 320U +/** @brief output of EMC CDB side A fixed (DIV4) divider */ +#define TEGRA234_CLK_EMCSA_EMC 321U +/** @brief output of EMC CDB side B fixed (DIV4) divider */ +#define TEGRA234_CLK_EMCSB_EMC 322U +/** @brief output of EMC CDB side C fixed (DIV4) divider */ +#define TEGRA234_CLK_EMCSC_EMC 323U +/** @brief output of EMC CDB side D fixed (DIV4) divider */ +#define TEGRA234_CLK_EMCSD_EMC 324U +/** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */ +#define TEGRA234_CLK_PLLE_HPS 326U +/** @brief CLK_ENB_PLLREFE_OUT gate output */ +#define TEGRA234_CLK_PLLREFE_VCOOUT_GATED 327U +/** @brief TEGRA234_CLK_SOR_SAFE clk source (PLLP_OUT0 divided by 17) */ +#define TEGRA234_CLK_PLLP_DIV17 328U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM switch divider output */ +#define TEGRA234_CLK_SOC_THERM 329U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENSE switch divider output */ +#define TEGRA234_CLK_TSENSE 330U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider free running clk */ +#define TEGRA234_CLK_FR_SEU1 331U +/** @brief NAFLL clock source for OFA */ +#define TEGRA234_CLK_NAFLL_OFA 333U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA switch divider output */ +#define TEGRA234_CLK_OFA 334U +/** @brief NAFLL clock source for SEU1 */ +#define TEGRA234_CLK_NAFLL_SEU1 335U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */ +#define TEGRA234_CLK_SEU1 336U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ +#define TEGRA234_CLK_SPI4 337U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI5 */ +#define TEGRA234_CLK_SPI5 338U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DCE_CPU_NIC */ +#define TEGRA234_CLK_DCE_CPU_NIC 339U +/** @brief output of divider CLK_RST_CONTROLLER_DCE_NIC_RATE */ +#define TEGRA234_CLK_DCE_NIC 340U +/** @brief NAFLL clock source for DCE */ +#define TEGRA234_CLK_NAFLL_DCE 341U +/** @brief Monitored branch of MPHY_L0_RX_ANA clock */ +#define TEGRA234_CLK_MPHY_L0_RX_ANA_M 342U +/** @brief Monitored branch of MPHY_L1_RX_ANA clock */ +#define TEGRA234_CLK_MPHY_L1_RX_ANA_M 343U +/** @brief ungated version of TX symbol clock after fixed 1/2 divider */ +#define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB 344U +/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ +#define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV 345U +/** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */ +#define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB 346U +/** @brief output of SW_MPHY_L0_TX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV 347U +/** @brief output of SW_MPHY_L0_TX_LS_3XBIT divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV 348U +/** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV 349U +/** @brief Monitored branch of MPHY_L0_TX_SYMB clock */ +#define TEGRA234_CLK_MPHY_L0_TX_SYMB_M 350U +/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ +#define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV 351U +/** @brief output of SW_MPHY_L0_RX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV 352U +/** @brief output of SW_MPHY_L0_RX_LS_BIT divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV 353U +/** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ +#define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV 354U +/** @brief Monitored branch of MPHY_L0_RX_SYMB clock */ +#define TEGRA234_CLK_MPHY_L0_RX_SYMB_M 355U /** @brief Monitored branch of MBGE0 RX input clock */ #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U /** @brief Monitored branch of MBGE1 RX input clock */ @@ -194,6 +670,14 @@ #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U /** @brief Monitored branch of MGBE3 RX PCS mux output */ #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH1 */ +#define TEGRA234_CLK_TACH1 365U +/** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */ +#define TEGRA234_CLK_MGBES_APP 366U +/** @brief Logical clk for setting GBE UPHY PLL2 TX_REF rate */ +#define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF 367U +/** @brief Logical clk for setting GBE UPHY PLL2 XDIG rate */ +#define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG 368U /** @brief RX PCS clock recovered from MGBE0 lane input */ #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U /** @brief RX PCS clock recovered from MGBE1 lane input */ @@ -230,6 +714,8 @@ #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ #define TEGRA234_CLK_MGBE1_MAC 386U +/** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE1_MACSEC 387U /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ #define TEGRA234_CLK_MGBE1_EEE_PCS 388U /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ @@ -246,6 +732,8 @@ #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ #define TEGRA234_CLK_MGBE2_MAC 395U +/** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE2_MACSEC 396U /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ #define TEGRA234_CLK_MGBE2_EEE_PCS 397U /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ @@ -270,9 +758,146 @@ #define TEGRA234_CLK_MGBE3_APP 407U /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ #define TEGRA234_CLK_MGBE3_PTP_REF 408U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_RX_BYP switch divider output */ +#define TEGRA234_CLK_GBE_RX_BYP_REF 409U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL0_MGMT switch divider output */ +#define TEGRA234_CLK_GBE_PLL0_MGMT 410U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL1_MGMT switch divider output */ +#define TEGRA234_CLK_GBE_PLL1_MGMT 411U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL2_MGMT switch divider output */ +#define TEGRA234_CLK_GBE_PLL2_MGMT 412U +/** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */ +#define TEGRA234_CLK_EQOS_MACSEC_RX 413U +/** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */ +#define TEGRA234_CLK_EQOS_MACSEC_TX 414U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider ungated output */ +#define TEGRA234_CLK_EQOS_TX_DIVIDER 415U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL1_MGMT switch divider output */ +#define TEGRA234_CLK_NVHS_PLL1_MGMT 416U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHUB mux output */ +#define TEGRA234_CLK_EMCHUB 417U +/** @brief clock recovered from I2S7 input */ +#define TEGRA234_CLK_I2S7_SYNC_INPUT 418U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S7 */ +#define TEGRA234_CLK_SYNC_I2S7 419U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S7 */ +#define TEGRA234_CLK_I2S7 420U +/** @brief Monitored output of I2S7 pad macro mux */ +#define TEGRA234_CLK_I2S7_PAD_M 421U +/** @brief clock recovered from I2S8 input */ +#define TEGRA234_CLK_I2S8_SYNC_INPUT 422U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S8 */ +#define TEGRA234_CLK_SYNC_I2S8 423U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S8 */ +#define TEGRA234_CLK_I2S8 424U +/** @brief Monitored output of I2S8 pad macro mux */ +#define TEGRA234_CLK_I2S8_PAD_M 425U +/** @brief NAFLL clock source for GPU GPC0 */ +#define TEGRA234_CLK_NAFLL_GPC0 426U +/** @brief NAFLL clock source for GPU GPC1 */ +#define TEGRA234_CLK_NAFLL_GPC1 427U +/** @brief NAFLL clock source for GPU SYSCLK */ +#define TEGRA234_CLK_NAFLL_GPUSYS 428U +/** @brief NAFLL clock source for CPU cluster 0 DSUCLK */ +#define TEGRA234_CLK_NAFLL_DSU0 429U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER0_DSU 429U +/** @brief NAFLL clock source for CPU cluster 1 DSUCLK */ +#define TEGRA234_CLK_NAFLL_DSU1 430U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER1_DSU 430U +/** @brief NAFLL clock source for CPU cluster 2 DSUCLK */ +#define TEGRA234_CLK_NAFLL_DSU2 431U /* TODO: remove */ +#define TEGRA234_CLK_NAFLL_CLUSTER2_DSU 431U +/** @brief output of gate CLK_ENB_SCE_CPU */ +#define TEGRA234_CLK_SCE_CPU 432U +/** @brief output of gate CLK_ENB_RCE_CPU */ +#define TEGRA234_CLK_RCE_CPU 433U +/** @brief output of gate CLK_ENB_DCE_CPU */ +#define TEGRA234_CLK_DCE_CPU 434U +/** @brief DSIPLL VCO output */ +#define TEGRA234_CLK_DSIPLL_VCO 435U +/** @brief DSIPLL SYNC_CLKOUTP/N differential output */ +#define TEGRA234_CLK_DSIPLL_CLKOUTPN 436U +/** @brief DSIPLL SYNC_CLKOUTA output */ +#define TEGRA234_CLK_DSIPLL_CLKOUTA 437U +/** @brief SPPLL0 VCO output */ +#define TEGRA234_CLK_SPPLL0_VCO 438U +/** @brief SPPLL0 SYNC_CLKOUTP/N differential output */ +#define TEGRA234_CLK_SPPLL0_CLKOUTPN 439U +/** @brief SPPLL0 SYNC_CLKOUTA output */ +#define TEGRA234_CLK_SPPLL0_CLKOUTA 440U +/** @brief SPPLL0 SYNC_CLKOUTB output */ +#define TEGRA234_CLK_SPPLL0_CLKOUTB 441U +/** @brief SPPLL0 CLKOUT_DIVBY10 output */ +#define TEGRA234_CLK_SPPLL0_DIV10 442U +/** @brief SPPLL0 CLKOUT_DIVBY25 output */ +#define TEGRA234_CLK_SPPLL0_DIV25 443U +/** @brief SPPLL0 CLKOUT_DIVBY27P/N differential output */ +#define TEGRA234_CLK_SPPLL0_DIV27PN 444U +/** @brief SPPLL1 VCO output */ +#define TEGRA234_CLK_SPPLL1_VCO 445U +/** @brief SPPLL1 SYNC_CLKOUTP/N differential output */ +#define TEGRA234_CLK_SPPLL1_CLKOUTPN 446U +/** @brief SPPLL1 CLKOUT_DIVBY27P/N differential output */ +#define TEGRA234_CLK_SPPLL1_DIV27PN 447U +/** @brief VPLL0 reference clock */ +#define TEGRA234_CLK_VPLL0_REF 448U +/** @brief VPLL0 */ +#define TEGRA234_CLK_VPLL0 449U +/** @brief VPLL1 */ +#define TEGRA234_CLK_VPLL1 450U +/** @brief NVDISPLAY_P0_CLK reference select */ +#define TEGRA234_CLK_NVDISPLAY_P0_REF 451U +/** @brief RG0_PCLK */ +#define TEGRA234_CLK_RG0 452U +/** @brief RG1_PCLK */ +#define TEGRA234_CLK_RG1 453U +/** @brief DISPPLL output */ +#define TEGRA234_CLK_DISPPLL 454U +/** @brief DISPHUBPLL output */ +#define TEGRA234_CLK_DISPHUBPLL 455U +/** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DIVIDER switch divider output (dsi_lp_clk) */ +#define TEGRA234_CLK_DSI_LP 456U /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ #define TEGRA234_CLK_AZA_2XBIT 457U /** @brief aza_2xbitclk / 2 (aza_bitclk) */ #define TEGRA234_CLK_AZA_BIT 458U +/** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE_CLK_SRC switch output (dsi_core_clk) */ +#define TEGRA234_CLK_DSI_CORE 459U +/** @brief Output of mux controlled by pkt_wr_fifo_signal from dsi (dsi_pixel_clk) */ +#define TEGRA234_CLK_DSI_PIXEL 460U +/** @brief Output of mux controlled by disp_2clk_sor0_dp_sel (pre_sor0_clk) */ +#define TEGRA234_CLK_PRE_SOR0 461U +/** @brief Output of mux controlled by disp_2clk_sor1_dp_sel (pre_sor1_clk) */ +#define TEGRA234_CLK_PRE_SOR1 462U +/** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG__0 output */ +#define TEGRA234_CLK_DP_LINK_REF 463U +/** @brief Link clock input from DP macro brick PLL */ +#define TEGRA234_CLK_SOR_LINKA_INPUT 464U +/** @brief SOR AFIFO clock outut */ +#define TEGRA234_CLK_SOR_LINKA_AFIFO 465U +/** @brief Monitored branch of linka_afifo_clk */ +#define TEGRA234_CLK_SOR_LINKA_AFIFO_M 466U +/** @brief Monitored branch of rg0_pclk */ +#define TEGRA234_CLK_RG0_M 467U +/** @brief Monitored branch of rg1_pclk */ +#define TEGRA234_CLK_RG1_M 468U +/** @brief Monitored branch of sor0_clk */ +#define TEGRA234_CLK_SOR0_M 469U +/** @brief Monitored branch of sor1_clk */ +#define TEGRA234_CLK_SOR1_M 470U +/** @brief EMC PLLHUB output */ +#define TEGRA234_CLK_PLLHUB 471U +/** @brief output of fixed (DIV2) MC HUB divider */ +#define TEGRA234_CLK_MCHUB 472U +/** @brief output of divider controlled by EMC side A MC_EMC_SAFE_SAME_FREQ */ +#define TEGRA234_CLK_EMCSA_MC 473U +/** @brief output of divider controlled by EMC side B MC_EMC_SAFE_SAME_FREQ */ +#define TEGRA234_CLK_EMCSB_MC 474U +/** @brief output of divider controlled by EMC side C MC_EMC_SAFE_SAME_FREQ */ +#define TEGRA234_CLK_EMCSC_MC 475U +/** @brief output of divider controlled by EMC side D MC_EMC_SAFE_SAME_FREQ */ +#define TEGRA234_CLK_EMCSD_MC 476U + +/** @} */ #endif diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index bd71cc1d7990..347e55e89a2a 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -8,31 +8,158 @@ #define TEGRA234_SID_INVALID 0x00 #define TEGRA234_SID_PASSTHROUGH 0x7f +/* ISO stream IDs */ +#define TEGRA234_SID_ISO_NVDISPLAY 0x01 +#define TEGRA234_SID_ISO_VI 0x02 +#define TEGRA234_SID_ISO_VIFALC 0x03 +#define TEGRA234_SID_ISO_VI2 0x04 +#define TEGRA234_SID_ISO_VI2FALC 0x05 +#define TEGRA234_SID_ISO_VI_VM2 0x06 +#define TEGRA234_SID_ISO_VI2_VM2 0x07 + /* NISO0 stream IDs */ -#define TEGRA234_SID_APE 0x02 -#define TEGRA234_SID_HDA 0x03 -#define TEGRA234_SID_GPCDMA 0x04 -#define TEGRA234_SID_MGBE 0x06 -#define TEGRA234_SID_PCIE0 0x12 -#define TEGRA234_SID_PCIE4 0x13 -#define TEGRA234_SID_PCIE5 0x14 -#define TEGRA234_SID_PCIE6 0x15 -#define TEGRA234_SID_PCIE9 0x1f -#define TEGRA234_SID_MGBE_VF1 0x49 -#define TEGRA234_SID_MGBE_VF2 0x4a -#define TEGRA234_SID_MGBE_VF3 0x4b +#define TEGRA234_SID_AON 0x01 +#define TEGRA234_SID_APE 0x02 +#define TEGRA234_SID_HDA 0x03 +#define TEGRA234_SID_GPCDMA 0x04 +#define TEGRA234_SID_ETR 0x05 +#define TEGRA234_SID_MGBE 0x06 +#define TEGRA234_SID_NVDISPLAY 0x07 +#define TEGRA234_SID_DCE 0x08 +#define TEGRA234_SID_PSC 0x09 +#define TEGRA234_SID_RCE 0x0a +#define TEGRA234_SID_SCE 0x0b +#define TEGRA234_SID_UFSHC 0x0c +#define TEGRA234_SID_APE_1 0x0d +#define TEGRA234_SID_GPCDMA_1 0x0e +#define TEGRA234_SID_GPCDMA_2 0x0f +#define TEGRA234_SID_GPCDMA_3 0x10 +#define TEGRA234_SID_GPCDMA_4 0x11 +#define TEGRA234_SID_PCIE0 0x12 +#define TEGRA234_SID_PCIE4 0x13 +#define TEGRA234_SID_PCIE5 0x14 +#define TEGRA234_SID_PCIE6 0x15 +#define TEGRA234_SID_RCE_VM2 0x16 +#define TEGRA234_SID_RCE_SERVER 0x17 +#define TEGRA234_SID_SMMU_TEST 0x18 +#define TEGRA234_SID_UFS_1 0x19 +#define TEGRA234_SID_UFS_2 0x1a +#define TEGRA234_SID_UFS_3 0x1b +#define TEGRA234_SID_UFS_4 0x1c +#define TEGRA234_SID_UFS_5 0x1d +#define TEGRA234_SID_UFS_6 0x1e +#define TEGRA234_SID_PCIE9 0x1f +#define TEGRA234_SID_VSE_GPCDMA_VM0 0x20 +#define TEGRA234_SID_VSE_GPCDMA_VM1 0x21 +#define TEGRA234_SID_VSE_GPCDMA_VM2 0x22 +#define TEGRA234_SID_NVDLA1 0x23 +#define TEGRA234_SID_NVENC 0x24 +#define TEGRA234_SID_NVJPG1 0x25 +#define TEGRA234_SID_OFA 0x26 +#define TEGRA234_SID_MGBE_VF1 0x49 +#define TEGRA234_SID_MGBE_VF2 0x4a +#define TEGRA234_SID_MGBE_VF3 0x4b +#define TEGRA234_SID_MGBE_VF4 0x4c +#define TEGRA234_SID_MGBE_VF5 0x4d +#define TEGRA234_SID_MGBE_VF6 0x4e +#define TEGRA234_SID_MGBE_VF7 0x4f +#define TEGRA234_SID_MGBE_VF8 0x50 +#define TEGRA234_SID_MGBE_VF9 0x51 +#define TEGRA234_SID_MGBE_VF10 0x52 +#define TEGRA234_SID_MGBE_VF11 0x53 +#define TEGRA234_SID_MGBE_VF12 0x54 +#define TEGRA234_SID_MGBE_VF13 0x55 +#define TEGRA234_SID_MGBE_VF14 0x56 +#define TEGRA234_SID_MGBE_VF15 0x57 +#define TEGRA234_SID_MGBE_VF16 0x58 +#define TEGRA234_SID_MGBE_VF17 0x59 +#define TEGRA234_SID_MGBE_VF18 0x5a +#define TEGRA234_SID_MGBE_VF19 0x5b +#define TEGRA234_SID_MGBE_VF20 0x5c +#define TEGRA234_SID_APE_2 0x5e +#define TEGRA234_SID_APE_3 0x5f +#define TEGRA234_SID_UFS_7 0x60 +#define TEGRA234_SID_UFS_8 0x61 +#define TEGRA234_SID_UFS_9 0x62 +#define TEGRA234_SID_UFS_10 0x63 +#define TEGRA234_SID_UFS_11 0x64 +#define TEGRA234_SID_UFS_12 0x65 +#define TEGRA234_SID_UFS_13 0x66 +#define TEGRA234_SID_UFS_14 0x67 +#define TEGRA234_SID_UFS_15 0x68 +#define TEGRA234_SID_UFS_16 0x69 +#define TEGRA234_SID_UFS_17 0x6a +#define TEGRA234_SID_UFS_18 0x6b +#define TEGRA234_SID_UFS_19 0x6c +#define TEGRA234_SID_UFS_20 0x6d +#define TEGRA234_SID_GPCDMA_5 0x6e +#define TEGRA234_SID_GPCDMA_6 0x6f +#define TEGRA234_SID_GPCDMA_7 0x70 +#define TEGRA234_SID_GPCDMA_8 0x71 +#define TEGRA234_SID_GPCDMA_9 0x72 /* NISO1 stream IDs */ -#define TEGRA234_SID_SDMMC4 0x02 -#define TEGRA234_SID_PCIE1 0x05 -#define TEGRA234_SID_PCIE2 0x06 -#define TEGRA234_SID_PCIE3 0x07 -#define TEGRA234_SID_PCIE7 0x08 -#define TEGRA234_SID_PCIE8 0x09 -#define TEGRA234_SID_PCIE10 0x0b -#define TEGRA234_SID_BPMP 0x10 -#define TEGRA234_SID_HOST1X 0x27 -#define TEGRA234_SID_VIC 0x34 +#define TEGRA234_SID_SDMMC1A 0x01 +#define TEGRA234_SID_SDMMC4 0x02 +#define TEGRA234_SID_EQOS 0x03 +#define TEGRA234_SID_HWMP_PMA 0x04 +#define TEGRA234_SID_PCIE1 0x05 +#define TEGRA234_SID_PCIE2 0x06 +#define TEGRA234_SID_PCIE3 0x07 +#define TEGRA234_SID_PCIE7 0x08 +#define TEGRA234_SID_PCIE8 0x09 +#define TEGRA234_SID_PCIE10 0x0b +#define TEGRA234_SID_QSPI0 0x0c +#define TEGRA234_SID_QSPI1 0x0d +#define TEGRA234_SID_XUSB_HOST 0x0e +#define TEGRA234_SID_XUSB_DEV 0x0f +#define TEGRA234_SID_BPMP 0x10 +#define TEGRA234_SID_FSI 0x11 +#define TEGRA234_SID_PVA0_VM0 0x12 +#define TEGRA234_SID_PVA0_VM1 0x13 +#define TEGRA234_SID_PVA0_VM2 0x14 +#define TEGRA234_SID_PVA0_VM3 0x15 +#define TEGRA234_SID_PVA0_VM4 0x16 +#define TEGRA234_SID_PVA0_VM5 0x17 +#define TEGRA234_SID_PVA0_VM6 0x18 +#define TEGRA234_SID_PVA0_VM7 0x19 +#define TEGRA234_SID_XUSB_VF0 0x1a +#define TEGRA234_SID_XUSB_VF1 0x1b +#define TEGRA234_SID_XUSB_VF2 0x1c +#define TEGRA234_SID_XUSB_VF3 0x1d +#define TEGRA234_SID_EQOS_VF1 0x1e +#define TEGRA234_SID_EQOS_VF2 0x1f +#define TEGRA234_SID_EQOS_VF3 0x20 +#define TEGRA234_SID_EQOS_VF4 0x21 +#define TEGRA234_SID_ISP_VM2 0x22 +#define TEGRA234_SID_HOST1X 0x27 +#define TEGRA234_SID_ISP 0x28 +#define TEGRA234_SID_NVDEC 0x29 +#define TEGRA234_SID_NVJPG 0x2a +#define TEGRA234_SID_NVDLA0 0x2b +#define TEGRA234_SID_PVA0 0x2c +#define TEGRA234_SID_SES_SE0 0x2d +#define TEGRA234_SID_SES_SE1 0x2e +#define TEGRA234_SID_SES_SE2 0x2f +#define TEGRA234_SID_SEU1_SE0 0x30 +#define TEGRA234_SID_SEU1_SE1 0x31 +#define TEGRA234_SID_SEU1_SE2 0x32 +#define TEGRA234_SID_TSEC 0x33 +#define TEGRA234_SID_VIC 0x34 +#define TEGRA234_SID_HC_VM0 0x3d +#define TEGRA234_SID_HC_VM1 0x3e +#define TEGRA234_SID_HC_VM2 0x3f +#define TEGRA234_SID_HC_VM3 0x40 +#define TEGRA234_SID_HC_VM4 0x41 +#define TEGRA234_SID_HC_VM5 0x42 +#define TEGRA234_SID_HC_VM6 0x43 +#define TEGRA234_SID_HC_VM7 0x44 +#define TEGRA234_SID_SE_VM0 0x45 +#define TEGRA234_SID_SE_VM1 0x46 +#define TEGRA234_SID_SE_VM2 0x47 +#define TEGRA234_SID_ISPFALC 0x48 +#define TEGRA234_SID_NISO1_SMMU_TEST 0x49 +#define TEGRA234_SID_TSEC_VM0 0x4a /* Shared stream IDs */ #define TEGRA234_SID_HOST1X_CTX0 0x35 @@ -48,21 +175,81 @@ * memory client IDs */ +/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ +#define TEGRA234_MEMORY_CLIENT_PTCR 0x00 +/* MSS internal memqual MIU7 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU7R 0x01 +/* MSS internal memqual MIU7 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU7W 0x02 +/* MSS internal memqual MIU8 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU8R 0x03 +/* MSS internal memqual MIU8 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU8W 0x04 +/* MSS internal memqual MIU9 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU9R 0x05 +/* MSS internal memqual MIU9 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU9W 0x06 +/* MSS internal memqual MIU10 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU10R 0x07 +/* MSS internal memqual MIU10 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU10W 0x08 +/* MSS internal memqual MIU11 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU11R 0x09 +/* MSS internal memqual MIU11 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a +/* MSS internal memqual MIU12 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b +/* MSS internal memqual MIU12 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c +/* MSS internal memqual MIU13 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d +/* MSS internal memqual MIU13 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e +#define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13 +#define TEGRA234_MEMORY_CLIENT_NVL5R 0x14 /* High-definition audio (HDA) read clients */ #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +/* Host channel data read clients */ #define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 +#define TEGRA234_MEMORY_CLIENT_NVL5W 0x17 +#define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18 +#define TEGRA234_MEMORY_CLIENT_NVL6R 0x19 +#define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a +#define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b +#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c +#define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d +#define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e +#define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20 +#define TEGRA234_MEMORY_CLIENT_NVL8R 0x21 +#define TEGRA234_MEMORY_CLIENT_NVL8W 0x22 +#define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23 +#define TEGRA234_MEMORY_CLIENT_NVL9R 0x24 +#define TEGRA234_MEMORY_CLIENT_NVL9W 0x25 /* PCIE6 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 /* PCIE6 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 /* PCIE7 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a +#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b +/* DLA0ARDB read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c +/* DLA0ARDB1 read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d +/* DLA0 writes */ +#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e +/* DLA1ARDB read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f /* PCIE7 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 /* PCIE8 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 /* High-definition audio (HDA) write clients */ #define TEGRA234_MEMORY_CLIENT_HDAW 0x35 +/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39 +/* OFAA client */ +#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a /* PCIE8 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b /* PCIE9 read clients */ @@ -75,10 +262,32 @@ #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f /* PCIE10 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 +/* ISP read client for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPRA 0x44 +/* ISP read client 1 for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45 +/* ISP Write client for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPWA 0x46 +/* ISP Write client Crossbar B */ +#define TEGRA234_MEMORY_CLIENT_ISPWB 0x47 /* PCIE10r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 /* PCIE7r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 +/* XUSB_HOST read clients */ +#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a +/* XUSB_HOST write clients */ +#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b +/* XUSB read clients */ +#define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c +/* XUSB_DEV write clients */ +#define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d +/* TSEC Memory Return Data Client Description */ +#define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54 +/* TSEC Memory Write Client Description */ +#define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55 +/* XSPI writes */ +#define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56 /* MGBE0 read client */ #define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 /* MGBEB read client */ @@ -89,18 +298,86 @@ #define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b /* MGBE0 write client */ #define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c +/* OFAA client */ +#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d +/* OFAA writes */ +#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e /* MGBEB write client */ #define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f +/* sdmmca memory read client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60 /* MGBEC write client */ #define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* sdmmca memory write client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64 /* MGBED write client */ #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 /* sdmmcd memory write client */ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 +/* SE Memory Return Data Client Description */ +#define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68 +/* SE Memory Write Client Description */ +#define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69 #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d +/* DLA1ARDB1 read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e +/* DLA1 writes */ +#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f +/* VI FLACON read clients */ +#define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71 +/* VI Write client */ +#define TEGRA234_MEMORY_CLIENT_VI2W 0x70 +/* VI Write client */ +#define TEGRA234_MEMORY_CLIENT_VIW 0x72 +/* NISO display read client */ +#define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73 +/* NVDISPNISO writes */ +#define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74 +/* XSPI client */ +#define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75 +/* XSPI writes */ +#define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76 +/* XSPI client */ +#define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77 +#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 +#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 +/* Audio Processing (APE) engine read clients */ +#define TEGRA234_MEMORY_CLIENT_APER 0x7a +/* Audio Processing (APE) engine write clients */ +#define TEGRA234_MEMORY_CLIENT_APEW 0x7b +/* VI2FAL writes */ +#define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c +#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e +#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f +/* SE Memory Return Data Client Description */ +#define TEGRA234_MEMORY_CLIENT_SESRD 0x80 +/* SE Memory Write Client Description */ +#define TEGRA234_MEMORY_CLIENT_SESWR 0x81 +/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ +#define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82 +/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ +#define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83 +/* ETR read clients */ +#define TEGRA234_MEMORY_CLIENT_ETRR 0x84 +/* ETR write clients */ +#define TEGRA234_MEMORY_CLIENT_ETRW 0x85 +/* AXI Switch read client */ +#define TEGRA234_MEMORY_CLIENT_AXISR 0x8c +/* AXI Switch write client */ +#define TEGRA234_MEMORY_CLIENT_AXISW 0x8d +/* EQOS read client */ +#define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e +/* EQOS write client */ +#define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f +/* UFSHC read client */ +#define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90 +/* UFSHC write client */ +#define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91 +/* NVDISPLAY read client */ +#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92 /* BPMP read client */ #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 /* BPMP write client */ @@ -109,10 +386,97 @@ #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 /* BPMPDMA write client */ #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 +/* AON read client */ +#define TEGRA234_MEMORY_CLIENT_AONR 0x97 +/* AON write client */ +#define TEGRA234_MEMORY_CLIENT_AONW 0x98 +/* AONDMA read client */ +#define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99 +/* AONDMA write client */ +#define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a +/* SCE read client */ +#define TEGRA234_MEMORY_CLIENT_SCER 0x9b +/* SCE write client */ +#define TEGRA234_MEMORY_CLIENT_SCEW 0x9c +/* SCEDMA read client */ +#define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d +/* SCEDMA write client */ +#define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e /* APEDMA read client */ #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f /* APEDMA write client */ #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 +/* NVDISPLAY read client instance 2 */ +#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1 +#define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2 +/* MSS internal memqual MIU0 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6 +/* MSS internal memqual MIU0 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7 +/* MSS internal memqual MIU1 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8 +/* MSS internal memqual MIU1 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9 +/* MSS internal memqual MIU2 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU2R 0xae +/* MSS internal memqual MIU2 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf +/* MSS internal memqual MIU3 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0 +/* MSS internal memqual MIU3 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1 +/* MSS internal memqual MIU4 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2 +/* MSS internal memqual MIU4 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3 +#define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4 +#define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5 +#define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6 +#define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7 +#define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8 +#define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9 +#define TEGRA234_MEMORY_CLIENT_NVL2R 0xba +#define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb +/* VI FLACON read clients */ +#define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc +/* VIFAL write clients */ +#define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd +/* DLA0ARDA read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe +/* DLA0 Falcon read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf +/* DLA0 write clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0 +/* DLA0 write clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1 +/* DLA1ARDA read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2 +/* DLA1 Falcon read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3 +/* DLA1 write clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4 +/* DLA1 write clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5 +/* PVA0RDA read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6 +/* PVA0RDB read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7 +/* PVA0RDC read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8 +/* PVA0WRA write clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9 +/* PVA0WRB write clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca +/* PVA0WRC write clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb +/* RCE read client */ +#define TEGRA234_MEMORY_CLIENT_RCER 0xd2 +/* RCE write client */ +#define TEGRA234_MEMORY_CLIENT_RCEW 0xd3 +/* RCEDMA read client */ +#define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4 +/* RCEDMA write client */ +#define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5 /* PCIE0 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 /* PCIE0 write clients */ @@ -137,7 +501,39 @@ #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 /* PCIE5 write clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 +/* ISP read client 1 for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4 +#define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5 +#define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6 +#define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7 +#define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8 +/* DLA0ARDA1 read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9 +/* DLA1ARDA1 read clients */ +#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea +/* PVA0RDA1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb +/* PVA0RDB1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec /* PCIE5r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef +#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0 +/* ISP read client for Crossbar A */ +#define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2 +#define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4 +#define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5 +#define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6 +#define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7 +#define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8 +/* MSS internal memqual MIU5 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc +/* MSS internal memqual MIU5 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd +/* MSS internal memqual MIU6 read clients */ +#define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe +/* MSS internal memqual MIU6 write clients */ +#define TEGRA234_MEMORY_CLIENT_MIU6W 0xff +#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 +#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 #endif diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index f5f82dde7399..1e19e258a74d 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -4,6 +4,16 @@ #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H #define _DT_BINDINGS_POWER_QCOM_RPMPD_H +/* SDM670 Power Domain Indexes */ +#define SDM670_MX 0 +#define SDM670_MX_AO 1 +#define SDM670_CX 2 +#define SDM670_CX_AO 3 +#define SDM670_LMX 4 +#define SDM670_LCX 5 +#define SDM670_GFX 6 +#define SDM670_MSS 7 + /* SDM845 Power Domain Indexes */ #define SDM845_EBI 0 #define SDM845_MX 1 @@ -103,6 +113,28 @@ #define SM8450_MXC_AO 11 #define SM8450_MSS 12 +/* SM8550 Power Domain Indexes */ +#define SM8550_CX 0 +#define SM8550_CX_AO 1 +#define SM8550_EBI 2 +#define SM8550_GFX 3 +#define SM8550_LCX 4 +#define SM8550_LMX 5 +#define SM8550_MMCX 6 +#define SM8550_MMCX_AO 7 +#define SM8550_MX 8 +#define SM8550_MX_AO 9 +#define SM8550_MXC 10 +#define SM8550_MXC_AO 11 +#define SM8550_MSS 12 +#define SM8550_NSP 13 + +/* QDU1000/QRU1000 Power Domain Indexes */ +#define QDU1000_EBI 0 +#define QDU1000_MSS 1 +#define QDU1000_CX 2 +#define QDU1000_MX 3 + /* SC7180 Power Domain Indexes */ #define SC7180_CX 0 #define SC7180_CX_AO 1 @@ -274,6 +306,16 @@ #define SDM660_SSCMX 8 #define SDM660_SSCMX_VFL 9 +/* SM4250 Power Domains */ +#define SM4250_VDDCX 0 +#define SM4250_VDDCX_AO 1 +#define SM4250_VDDCX_VFL 2 +#define SM4250_VDDMX 3 +#define SM4250_VDDMX_AO 4 +#define SM4250_VDDMX_VFL 5 +#define SM4250_VDD_LPI_CX 6 +#define SM4250_VDD_LPI_MX 7 + /* SM6115 Power Domains */ #define SM6115_VDDCX 0 #define SM6115_VDDCX_AO 1 diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index ae9286cef85c..b0fec2ddec84 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -4,6 +4,7 @@ #ifndef __ABI_MACH_T234_POWERGATE_T234_H_ #define __ABI_MACH_T234_POWERGATE_T234_H_ +#define TEGRA234_POWER_DOMAIN_OFA 1U #define TEGRA234_POWER_DOMAIN_AUD 2U #define TEGRA234_POWER_DOMAIN_DISP 3U #define TEGRA234_POWER_DOMAIN_PCIEX8A 5U @@ -11,6 +12,9 @@ #define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U #define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U #define TEGRA234_POWER_DOMAIN_PCIEX1A 9U +#define TEGRA234_POWER_DOMAIN_XUSBA 10U +#define TEGRA234_POWER_DOMAIN_XUSBB 11U +#define TEGRA234_POWER_DOMAIN_XUSBC 12U #define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U #define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U #define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U @@ -19,6 +23,17 @@ #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U #define TEGRA234_POWER_DOMAIN_MGBED 20U +#define TEGRA234_POWER_DOMAIN_ISPA 22U +#define TEGRA234_POWER_DOMAIN_NVDEC 23U +#define TEGRA234_POWER_DOMAIN_NVJPGA 24U +#define TEGRA234_POWER_DOMAIN_NVENC 25U +#define TEGRA234_POWER_DOMAIN_VI 28U #define TEGRA234_POWER_DOMAIN_VIC 29U +#define TEGRA234_POWER_DOMAIN_PVA 30U +#define TEGRA234_POWER_DOMAIN_DLAA 32U +#define TEGRA234_POWER_DOMAIN_DLAB 33U +#define TEGRA234_POWER_DOMAIN_CV 34U +#define TEGRA234_POWER_DOMAIN_GPU 35U +#define TEGRA234_POWER_DOMAIN_NVJPGB 36U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index d48d22b2bc7f..85cc423a7bdf 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -10,14 +10,29 @@ * @brief Identifiers for Resets controllable by firmware * @{ */ +#define TEGRA234_RESET_ACTMON 1U +#define TEGRA234_RESET_ADSP_ALL 2U +#define TEGRA234_RESET_DSI_CORE 3U +#define TEGRA234_RESET_CAN1 4U +#define TEGRA234_RESET_CAN2 5U +#define TEGRA234_RESET_DLA0 6U +#define TEGRA234_RESET_DLA1 7U +#define TEGRA234_RESET_DPAUX 8U +#define TEGRA234_RESET_OFA 9U +#define TEGRA234_RESET_NVJPG1 10U #define TEGRA234_RESET_PEX1_CORE_6 11U #define TEGRA234_RESET_PEX1_CORE_6_APB 12U #define TEGRA234_RESET_PEX1_COMMON_APB 13U #define TEGRA234_RESET_PEX2_CORE_7 14U #define TEGRA234_RESET_PEX2_CORE_7_APB 15U +#define TEGRA234_RESET_NVDISPLAY 16U +#define TEGRA234_RESET_EQOS 17U #define TEGRA234_RESET_GPCDMA 18U +#define TEGRA234_RESET_GPU 19U #define TEGRA234_RESET_HDA 20U #define TEGRA234_RESET_HDACODEC 21U +#define TEGRA234_RESET_EQOS_MACSEC 22U +#define TEGRA234_RESET_EQOS_MACSEC_SECURE 23U #define TEGRA234_RESET_I2C1 24U #define TEGRA234_RESET_PEX2_CORE_8 25U #define TEGRA234_RESET_PEX2_CORE_8_APB 26U @@ -30,15 +45,36 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_ISP 36U +#define TEGRA234_RESET_MIPI_CAL 37U +#define TEGRA234_RESET_MPHY_CLK_CTL 38U +#define TEGRA234_RESET_MPHY_L0_RX 39U +#define TEGRA234_RESET_MPHY_L0_TX 40U +#define TEGRA234_RESET_MPHY_L1_RX 41U +#define TEGRA234_RESET_MPHY_L1_TX 42U +#define TEGRA234_RESET_NVCSI 43U +#define TEGRA234_RESET_NVDEC 44U #define TEGRA234_RESET_MGBE0_PCS 45U #define TEGRA234_RESET_MGBE0_MAC 46U +#define TEGRA234_RESET_MGBE0_MACSEC 47U +#define TEGRA234_RESET_MGBE0_MACSEC_SECURE 48U #define TEGRA234_RESET_MGBE1_PCS 49U #define TEGRA234_RESET_MGBE1_MAC 50U +#define TEGRA234_RESET_MGBE1_MACSEC 51U +#define TEGRA234_RESET_MGBE1_MACSEC_SECURE 52U #define TEGRA234_RESET_MGBE2_PCS 53U #define TEGRA234_RESET_MGBE2_MAC 54U +#define TEGRA234_RESET_MGBE2_MACSEC 55U #define TEGRA234_RESET_PEX2_CORE_10 56U #define TEGRA234_RESET_PEX2_CORE_10_APB 57U #define TEGRA234_RESET_PEX2_COMMON_APB 58U +#define TEGRA234_RESET_NVENC 59U +#define TEGRA234_RESET_MGBE2_MACSEC_SECURE 60U +#define TEGRA234_RESET_NVJPG 61U +#define TEGRA234_RESET_LA 64U +#define TEGRA234_RESET_HWPM 65U +#define TEGRA234_RESET_PVA0_ALL 66U +#define TEGRA234_RESET_CEC 67U #define TEGRA234_RESET_PWM1 68U #define TEGRA234_RESET_PWM2 69U #define TEGRA234_RESET_PWM3 70U @@ -49,11 +85,43 @@ #define TEGRA234_RESET_PWM8 75U #define TEGRA234_RESET_QSPI0 76U #define TEGRA234_RESET_QSPI1 77U +#define TEGRA234_RESET_I2S7 78U +#define TEGRA234_RESET_I2S8 79U +#define TEGRA234_RESET_SCE_ALL 80U +#define TEGRA234_RESET_RCE_ALL 81U +#define TEGRA234_RESET_SDMMC1 82U +#define TEGRA234_RESET_RSVD_83 83U +#define TEGRA234_RESET_RSVD_84 84U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_MGBE3_PCS 87U #define TEGRA234_RESET_MGBE3_MAC 88U +#define TEGRA234_RESET_MGBE3_MACSEC 89U +#define TEGRA234_RESET_MGBE3_MACSEC_SECURE 90U +#define TEGRA234_RESET_SPI1 91U +#define TEGRA234_RESET_SPI2 92U +#define TEGRA234_RESET_SPI3 93U +#define TEGRA234_RESET_SPI4 94U +#define TEGRA234_RESET_TACH0 95U +#define TEGRA234_RESET_TACH1 96U +#define TEGRA234_RESET_SPI5 97U +#define TEGRA234_RESET_TSEC 98U +#define TEGRA234_RESET_UARTI 99U #define TEGRA234_RESET_UARTA 100U -#define TEGRA234_RESET_VIC 113U +#define TEGRA234_RESET_UARTB 101U +#define TEGRA234_RESET_UARTC 102U +#define TEGRA234_RESET_UARTD 103U +#define TEGRA234_RESET_UARTE 104U +#define TEGRA234_RESET_UARTF 105U +#define TEGRA234_RESET_UARTJ 106U +#define TEGRA234_RESET_UARTH 107U +#define TEGRA234_RESET_UFSHC 108U +#define TEGRA234_RESET_UFSHC_AXI_M 109U +#define TEGRA234_RESET_UFSHC_LP_SEQ 110U +#define TEGRA234_RESET_RSVD_111 111U +#define TEGRA234_RESET_VI 112U +#define TEGRA234_RESET_VIC 113U +#define TEGRA234_RESET_XUSB_PADCTL 114U +#define TEGRA234_RESET_VI2 115U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U #define TEGRA234_RESET_PEX0_CORE_2 118U @@ -65,8 +133,49 @@ #define TEGRA234_RESET_PEX0_CORE_3_APB 124U #define TEGRA234_RESET_PEX0_CORE_4_APB 125U #define TEGRA234_RESET_PEX0_COMMON_APB 126U +#define TEGRA234_RESET_RSVD_127 127U +#define TEGRA234_RESET_NVHS_UPHY_PLL1 128U #define TEGRA234_RESET_PEX1_CORE_5 129U #define TEGRA234_RESET_PEX1_CORE_5_APB 130U +#define TEGRA234_RESET_GBE_UPHY 131U +#define TEGRA234_RESET_GBE_UPHY_PM 132U +#define TEGRA234_RESET_NVHS_UPHY 133U +#define TEGRA234_RESET_NVHS_UPHY_PLL0 134U +#define TEGRA234_RESET_NVHS_UPHY_L0 135U +#define TEGRA234_RESET_NVHS_UPHY_L1 136U +#define TEGRA234_RESET_NVHS_UPHY_L2 137U +#define TEGRA234_RESET_NVHS_UPHY_L3 138U +#define TEGRA234_RESET_NVHS_UPHY_L4 139U +#define TEGRA234_RESET_NVHS_UPHY_L5 140U +#define TEGRA234_RESET_NVHS_UPHY_L6 141U +#define TEGRA234_RESET_NVHS_UPHY_L7 142U +#define TEGRA234_RESET_NVHS_UPHY_PM 143U +#define TEGRA234_RESET_DMIC5 144U +#define TEGRA234_RESET_APE 145U +#define TEGRA234_RESET_PEX_USB_UPHY 146U +#define TEGRA234_RESET_PEX_USB_UPHY_L0 147U +#define TEGRA234_RESET_PEX_USB_UPHY_L1 148U +#define TEGRA234_RESET_PEX_USB_UPHY_L2 149U +#define TEGRA234_RESET_PEX_USB_UPHY_L3 150U +#define TEGRA234_RESET_PEX_USB_UPHY_L4 151U +#define TEGRA234_RESET_PEX_USB_UPHY_L5 152U +#define TEGRA234_RESET_PEX_USB_UPHY_L6 153U +#define TEGRA234_RESET_PEX_USB_UPHY_L7 154U +#define TEGRA234_RESET_PEX_USB_UPHY_PLL0 159U +#define TEGRA234_RESET_PEX_USB_UPHY_PLL1 160U +#define TEGRA234_RESET_PEX_USB_UPHY_PLL2 161U +#define TEGRA234_RESET_PEX_USB_UPHY_PLL3 162U +#define TEGRA234_RESET_GBE_UPHY_L0 163U +#define TEGRA234_RESET_GBE_UPHY_L1 164U +#define TEGRA234_RESET_GBE_UPHY_L2 165U +#define TEGRA234_RESET_GBE_UPHY_L3 166U +#define TEGRA234_RESET_GBE_UPHY_L4 167U +#define TEGRA234_RESET_GBE_UPHY_L5 168U +#define TEGRA234_RESET_GBE_UPHY_L6 169U +#define TEGRA234_RESET_GBE_UPHY_L7 170U +#define TEGRA234_RESET_GBE_UPHY_PLL0 171U +#define TEGRA234_RESET_GBE_UPHY_PLL1 172U +#define TEGRA234_RESET_GBE_UPHY_PLL2 173U /** @} */ diff --git a/include/linux/bcm47xx_nvram.h b/include/linux/bcm47xx_nvram.h index 53b31f69b74a..7615f8d7b1ed 100644 --- a/include/linux/bcm47xx_nvram.h +++ b/include/linux/bcm47xx_nvram.h @@ -11,6 +11,7 @@ #include <linux/vmalloc.h> #ifdef CONFIG_BCM47XX_NVRAM +int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size); int bcm47xx_nvram_init_from_mem(u32 base, u32 lim); int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len); int bcm47xx_nvram_gpio_pin(const char *name); @@ -20,6 +21,11 @@ static inline void bcm47xx_nvram_release_contents(char *nvram) vfree(nvram); }; #else +static inline int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, + size_t res_size) +{ + return -ENOTSUPP; +} static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim) { return -ENOTSUPP; diff --git a/include/linux/platform_data/gpmc-omap.h b/include/linux/platform_data/gpmc-omap.h index c9cc4e32435d..dcca6c5e23bb 100644 --- a/include/linux/platform_data/gpmc-omap.h +++ b/include/linux/platform_data/gpmc-omap.h @@ -136,6 +136,13 @@ struct gpmc_device_timings { #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */ #define GPMC_MUX_AD 2 /* Addr-Data multiplex */ +/* Wait pin polarity values */ +#define GPMC_WAITPINPOLARITY_INVALID UINT_MAX +#define GPMC_WAITPINPOLARITY_ACTIVE_LOW 0 +#define GPMC_WAITPINPOLARITY_ACTIVE_HIGH 1 + +#define GPMC_WAITPIN_INVALID UINT_MAX + struct gpmc_settings { bool burst_wrap; /* enables wrap bursting */ bool burst_read; /* enables read page/burst mode */ @@ -149,6 +156,7 @@ struct gpmc_settings { u32 device_width; /* device bus width (8 or 16 bit) */ u32 mux_add_data; /* multiplex address & data */ u32 wait_pin; /* wait-pin to be used */ + u32 wait_pin_polarity; }; /* Data for each chip select */ diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index ebc351698090..1cd41bdf73cf 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -17,6 +17,7 @@ #include <linux/notifier.h> #include <linux/spinlock.h> #include <linux/cpumask.h> +#include <linux/time64.h> /* * Flags to control the behaviour of a genpd. @@ -95,6 +96,7 @@ struct genpd_governor_data { s64 max_off_time_ns; bool max_off_time_changed; ktime_t next_wakeup; + ktime_t next_hrtimer; bool cached_power_down_ok; bool cached_power_down_state_idx; }; @@ -232,6 +234,7 @@ int dev_pm_genpd_set_performance_state(struct device *dev, unsigned int state); int dev_pm_genpd_add_notifier(struct device *dev, struct notifier_block *nb); int dev_pm_genpd_remove_notifier(struct device *dev); void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next); +ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev); extern struct dev_power_governor simple_qos_governor; extern struct dev_power_governor pm_domain_always_on_gov; @@ -293,6 +296,10 @@ static inline int dev_pm_genpd_remove_notifier(struct device *dev) static inline void dev_pm_genpd_set_next_wakeup(struct device *dev, ktime_t next) { } +static inline ktime_t dev_pm_genpd_get_next_hrtimer(struct device *dev) +{ + return KTIME_MAX; +} #define simple_qos_governor (*(struct dev_power_governor *)(NULL)) #define pm_domain_always_on_gov (*(struct dev_power_governor *)(NULL)) #endif diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index d2b02bb43768..b85f66db33e1 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -9,6 +9,13 @@ enum mtk_ddp_comp_id; struct device; +enum mtk_dpi_out_format_con { + MTK_DPI_RGB888_SDR_CON, + MTK_DPI_RGB888_DDR_CON, + MTK_DPI_RGB565_SDR_CON, + MTK_DPI_RGB565_DDR_CON +}; + enum mtk_ddp_comp_id { DDP_COMPONENT_AAL0, DDP_COMPONENT_AAL1, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index bc2fb8343a94..ad1fd718169d 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -42,7 +42,19 @@ #define LLCC_CPUHWT 36 #define LLCC_MDMCLAD2 37 #define LLCC_CAMEXP1 38 +#define LLCC_CMPTHCP 39 +#define LLCC_LCPDARE 40 #define LLCC_AENPU 45 +#define LLCC_ISLAND1 46 +#define LLCC_ISLAND2 47 +#define LLCC_ISLAND3 48 +#define LLCC_ISLAND4 49 +#define LLCC_CAMEXP2 50 +#define LLCC_CAMEXP3 51 +#define LLCC_CAMEXP4 52 +#define LLCC_DISP_WB 53 +#define LLCC_DISP_1 54 +#define LLCC_VIDVSP 64 /** * struct llcc_slice_desc - Cache slice descriptor diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h index 9c0ad64b8d29..862eff613dc7 100644 --- a/include/memory/renesas-rpc-if.h +++ b/include/memory/renesas-rpc-if.h @@ -59,6 +59,7 @@ struct rpcif_op { enum rpcif_type { RPCIF_RCAR_GEN3, + RPCIF_RCAR_GEN4, RPCIF_RZ_G2L, }; diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index b02e9fe69146..eb5079904cc8 100644 --- a/include/soc/fsl/qe/qe.h +++ b/include/soc/fsl/qe/qe.h @@ -172,14 +172,15 @@ static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } /* * Pin multiplexing functions. */ +struct device; struct qe_pin; #ifdef CONFIG_QE_GPIO -extern struct qe_pin *qe_pin_request(struct device_node *np, int index); +extern struct qe_pin *qe_pin_request(struct device *dev, int index); extern void qe_pin_free(struct qe_pin *qe_pin); extern void qe_pin_set_gpio(struct qe_pin *qe_pin); extern void qe_pin_set_dedicated(struct qe_pin *pin); #else -static inline struct qe_pin *qe_pin_request(struct device_node *np, int index) +static inline struct qe_pin *qe_pin_request(struct device *dev, int index) { return ERR_PTR(-ENOSYS); } diff --git a/include/soc/qcom/qcom-spmi-pmic.h b/include/soc/qcom/qcom-spmi-pmic.h index 72398ff44719..c47cc71a999e 100644 --- a/include/soc/qcom/qcom-spmi-pmic.h +++ b/include/soc/qcom/qcom-spmi-pmic.h @@ -26,18 +26,29 @@ #define PM8901_SUBTYPE 0x0f #define PM8950_SUBTYPE 0x10 #define PMI8950_SUBTYPE 0x11 +#define PMK8001_SUBTYPE 0x12 +#define PMI8996_SUBTYPE 0x13 #define PM8998_SUBTYPE 0x14 #define PMI8998_SUBTYPE 0x15 #define PM8005_SUBTYPE 0x18 -#define PM660L_SUBTYPE 0x1A -#define PM660_SUBTYPE 0x1B -#define PM8150_SUBTYPE 0x1E +#define PM660L_SUBTYPE 0x1a +#define PM660_SUBTYPE 0x1b +#define PM8150_SUBTYPE 0x1e #define PM8150L_SUBTYPE 0x1f #define PM8150B_SUBTYPE 0x20 #define PMK8002_SUBTYPE 0x21 #define PM8009_SUBTYPE 0x24 +#define PMI632_SUBTYPE 0x25 #define PM8150C_SUBTYPE 0x26 +#define PM6150_SUBTYPE 0x28 #define SMB2351_SUBTYPE 0x29 +#define PM8008_SUBTYPE 0x2c +#define PM6125_SUBTYPE 0x2d +#define PM7250B_SUBTYPE 0x2e +#define PMK8350_SUBTYPE 0x2f +#define PMR735B_SUBTYPE 0x34 +#define PM6350_SUBTYPE 0x36 +#define PM2250_SUBTYPE 0x37 #define PMI8998_FAB_ID_SMIC 0x11 #define PMI8998_FAB_ID_GF 0x30 diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h index 53171e324d1c..ecefcaec7e66 100644 --- a/include/soc/tegra/bpmp-abi.h +++ b/include/soc/tegra/bpmp-abi.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef ABI_BPMP_ABI_H @@ -74,6 +74,32 @@ /** * @ingroup MRQ_Format + * Request an answer from the peer. + * This should be set in mrq_request::flags for all requests targetted + * at BPMP. For requests originating in BPMP, this flag is optional except + * for messages targeting MCE, for which the field must be set. + * When this flag is not set, the remote peer must not send a response + * back. + */ +#define BPMP_MAIL_DO_ACK (1U << 0U) + +/** + * @ingroup MRQ_Format + * Ring the sender's doorbell when responding. This should be set unless + * the sender wants to poll the underlying communications layer directly. + * + * An optional direction that can be specified in mrq_request::flags. + */ +#define BPMP_MAIL_RING_DB (1U << 1U) + +/** + * @ingroup MRQ_Format + * CRC present + */ +#define BPMP_MAIL_CRC_PRESENT (1U << 2U) + +/** + * @ingroup MRQ_Format * @brief Header for an MRQ message * * Provides the MRQ number for the MRQ message: #mrq. The remainder of @@ -85,12 +111,139 @@ struct mrq_request { uint32_t mrq; /** - * @brief Flags providing follow up directions to the receiver + * @brief 32bit word containing a number of fields as follows: + * + * struct { + * uint8_t options:4; + * uint8_t xid:4; + * uint8_t payload_length; + * uint16_t crc16; + * }; + * + * **options** directions to the receiver and indicates CRC presence. + * + * #BPMP_MAIL_DO_ACK and #BPMP_MAIL_RING_DB see documentation of respective options. + * #BPMP_MAIL_CRC_PRESENT is supported on T234 and later platforms. It indicates the + * crc16, xid and length fields are present when set. + * Some platform configurations, especially when targeted to applications requiring + * functional safety, mandate this option being set or otherwise will respond with + * -BPMP_EBADMSG and ignore the request. + * + * **xid** is a transaction ID. + * + * Only used when #BPMP_MAIL_CRC_PRESENT is set. + * + * **payload_length** of the message expressed in bytes without the size of this header. + * See table below for minimum accepted payload lengths for each MRQ. + * Note: For DMCE communication, this field expresses the length as a multiple of 4 bytes + * rather than bytes. + * + * Only used when #BPMP_MAIL_CRC_PRESENT is set. + * + * | MRQ | CMD | minimum payload length + * | -------------------- | ------------------------------------ | ------------------------------------------ | + * | MRQ_PING | | 4 | + * | MRQ_THREADED_PING | | 4 | + * | MRQ_RESET | any | 8 | + * | MRQ_I2C | | 12 + cmd_i2c_xfer_request.data_size | + * | MRQ_CLK | CMD_CLK_GET_RATE | 4 | + * | MRQ_CLK | CMD_CLK_SET_RATE | 16 | + * | MRQ_CLK | CMD_CLK_ROUND_RATE | 16 | + * | MRQ_CLK | CMD_CLK_GET_PARENT | 4 | + * | MRQ_CLK | CMD_CLK_SET_PARENT | 8 | + * | MRQ_CLK | CMD_CLK_ENABLE | 4 | + * | MRQ_CLK | CMD_CLK_DISABLE | 4 | + * | MRQ_CLK | CMD_CLK_IS_ENABLED | 4 | + * | MRQ_CLK | CMD_CLK_GET_ALL_INFO | 4 | + * | MRQ_CLK | CMD_CLK_GET_MAX_CLK_ID | 4 | + * | MRQ_CLK | CMD_CLK_GET_FMAX_AT_VMIN | 4 | + * | MRQ_QUERY_ABI | | 4 | + * | MRQ_PG | CMD_PG_QUERY_ABI | 12 | + * | MRQ_PG | CMD_PG_SET_STATE | 12 | + * | MRQ_PG | CMD_PG_GET_STATE | 8 | + * | MRQ_PG | CMD_PG_GET_NAME | 8 | + * | MRQ_PG | CMD_PG_GET_MAX_ID | 8 | + * | MRQ_THERMAL | CMD_THERMAL_QUERY_ABI | 8 | + * | MRQ_THERMAL | CMD_THERMAL_GET_TEMP | 8 | + * | MRQ_THERMAL | CMD_THERMAL_SET_TRIP | 20 | + * | MRQ_THERMAL | CMD_THERMAL_GET_NUM_ZONES | 4 | + * | MRQ_THERMAL | CMD_THERMAL_GET_THERMTRIP | 8 | + * | MRQ_CPU_VHINT | | 8 | + * | MRQ_ABI_RATCHET | | 2 | + * | MRQ_EMC_DVFS_LATENCY | | 8 | + * | MRQ_EMC_DVFS_EMCHUB | | 8 | + * | MRQ_EMC_DISP_RFL | | 4 | + * | MRQ_BWMGR | CMD_BWMGR_QUERY_ABI | 8 | + * | MRQ_BWMGR | CMD_BWMGR_CALC_RATE | 8 + 8 * bwmgr_rate_req.num_iso_clients | + * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_QUERY_ABI | 8 | + * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_CALCULATE_LA | 16 | + * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_SET_LA | 16 | + * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_GET_MAX_BW | 8 | + * | MRQ_CPU_NDIV_LIMITS | | 4 | + * | MRQ_CPU_AUTO_CC3 | | 4 | + * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_QUERY_ABI | 8 | + * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_READ | 5 | + * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_WRITE | 5 + cmd_ringbuf_console_write_req.len | + * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_GET_FIFO | 4 | + * | MRQ_STRAP | STRAP_SET | 12 | + * | MRQ_UPHY | CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | 24 | + * | MRQ_UPHY | CMD_UPHY_PCIE_LANE_MARGIN_STATUS | 4 | + * | MRQ_UPHY | CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT | 5 | + * | MRQ_UPHY | CMD_UPHY_PCIE_CONTROLLER_STATE | 6 | + * | MRQ_UPHY | CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF | 5 | + * | MRQ_FMON | CMD_FMON_GEAR_CLAMP | 16 | + * | MRQ_FMON | CMD_FMON_GEAR_FREE | 4 | + * | MRQ_FMON | CMD_FMON_GEAR_GET | 4 | + * | MRQ_FMON | CMD_FMON_FAULT_STS_GET | 8 | + * | MRQ_EC | CMD_EC_STATUS_EX_GET | 12 | + * | MRQ_QUERY_FW_TAG | | 0 | + * | MRQ_DEBUG | CMD_DEBUG_OPEN_RO | 4 + length of cmd_debug_fopen_request.name | + * | MRQ_DEBUG | CMD_DEBUG_OPEN_WO | 4 + length of cmd_debug_fopen_request.name | + * | MRQ_DEBUG | CMD_DEBUG_READ | 8 | + * | MRQ_DEBUG | CMD_DEBUG_WRITE | 12 + cmd_debug_fwrite_request.datalen | + * | MRQ_DEBUG | CMD_DEBUG_CLOSE | 8 | + * | MRQ_TELEMETRY | | 8 | + * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_QUERY_ABI | 8 | + * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_SET | 20 | + * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_GET | 16 | + * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_CURR_CAP | 8 | + * | MRQ_GEARS | | 0 | + * | MRQ_BWMGR_INT | CMD_BWMGR_INT_QUERY_ABI | 8 | + * | MRQ_BWMGR_INT | CMD_BWMGR_INT_CALC_AND_SET | 16 | + * | MRQ_BWMGR_INT | CMD_BWMGR_INT_CAP_SET | 8 | + * | MRQ_OC_STATUS | | 0 | + * + * **crc16** + * + * CRC16 using polynomial x^16 + x^14 + x^12 + x^11 + x^8 + x^5 + x^4 + x^2 + 1 + * and initialization value 0x4657. The CRC is calculated over all bytes of the message + * including this header. However the crc16 field is considered to be set to 0 when + * calculating the CRC. Only used when #BPMP_MAIL_CRC_PRESENT is set. If + * #BPMP_MAIL_CRC_PRESENT is set and this field does not match the CRC as + * calculated by BPMP, -BPMP_EBADMSG will be returned and the request will + * be ignored. See code snippet below on how to calculate the CRC. * - * | Bit | Description | - * |-----|--------------------------------------------| - * | 1 | ring the sender's doorbell when responding | - * | 0 | should be 1 | + * @code + * uint16_t calc_crc_digest(uint16_t crc, uint8_t *data, size_t size) + * { + * for (size_t i = 0; i < size; i++) { + * crc ^= data[i] << 8; + * for (size_t j = 0; j < 8; j++) { + * if ((crc & 0x8000) == 0x8000) { + * crc = (crc << 1) ^ 0xAC9A; + * } else { + * crc = (crc << 1); + * } + * } + * } + * return crc; + * } + * + * uint16_t calc_crc(uint8_t *data, size_t size) + * { + * return calc_crc_digest(0x4657, data, size); + * } + * @endcode */ uint32_t flags; } BPMP_ABI_PACKED; @@ -107,7 +260,35 @@ struct mrq_request { struct mrq_response { /** @brief Error code for the MRQ request itself */ int32_t err; - /** @brief Reserved for future use */ + + /** + * @brief 32bit word containing a number of fields as follows: + * + * struct { + * uint8_t options:4; + * uint8_t xid:4; + * uint8_t payload_length; + * uint16_t crc16; + * }; + * + * **options** indicates CRC presence. + * + * #BPMP_MAIL_CRC_PRESENT is supported on T234 and later platforms and + * indicates the crc16 related fields are present when set. + * + * **xid** is the transaction ID as sent by the requestor. + * + * **length** of the message expressed in bytes without the size of this header. + * Note: For DMCE communication, this field expresses the length as a multiple of 4 bytes + * rather than bytes. + * + * **crc16** + * + * CRC16 using polynomial x^16 + x^14 + x^12 + x^11 + x^8 + x^5 + x^4 + x^2 + 1 + * and initialization value 0x4657. The CRC is calculated over all bytes of the message + * including this header. However the crc16 field is considered to be set to 0 when + * calculating the CRC. Only used when #BPMP_MAIL_CRC_PRESENT is set. + */ uint32_t flags; } BPMP_ABI_PACKED; @@ -131,24 +312,16 @@ struct mrq_response { #define MRQ_PING 0U #define MRQ_QUERY_TAG 1U -#define MRQ_MODULE_LOAD 4U -#define MRQ_MODULE_UNLOAD 5U -#define MRQ_TRACE_MODIFY 7U -#define MRQ_WRITE_TRACE 8U #define MRQ_THREADED_PING 9U -#define MRQ_MODULE_MAIL 11U #define MRQ_DEBUGFS 19U #define MRQ_RESET 20U #define MRQ_I2C 21U #define MRQ_CLK 22U #define MRQ_QUERY_ABI 23U -#define MRQ_PG_READ_STATE 25U -#define MRQ_PG_UPDATE_STATE 26U #define MRQ_THERMAL 27U #define MRQ_CPU_VHINT 28U #define MRQ_ABI_RATCHET 29U #define MRQ_EMC_DVFS_LATENCY 31U -#define MRQ_TRACE_ITER 64U #define MRQ_RINGBUF_CONSOLE 65U #define MRQ_PG 66U #define MRQ_CPU_NDIV_LIMITS 67U @@ -159,6 +332,40 @@ struct mrq_response { #define MRQ_FMON 72U #define MRQ_EC 73U #define MRQ_DEBUG 75U +#define MRQ_EMC_DVFS_EMCHUB 76U +#define MRQ_BWMGR 77U +#define MRQ_ISO_CLIENT 78U +#define MRQ_EMC_DISP_RFL 79U +#define MRQ_TELEMETRY 80U +#define MRQ_PWR_LIMIT 81U +#define MRQ_GEARS 82U +#define MRQ_BWMGR_INT 83U +#define MRQ_OC_STATUS 84U + +/** @cond DEPRECATED */ +#define MRQ_RESERVED_2 2U +#define MRQ_RESERVED_3 3U +#define MRQ_RESERVED_4 4U +#define MRQ_RESERVED_5 5U +#define MRQ_RESERVED_6 6U +#define MRQ_RESERVED_7 7U +#define MRQ_RESERVED_8 8U +#define MRQ_RESERVED_10 10U +#define MRQ_RESERVED_11 11U +#define MRQ_RESERVED_12 12U +#define MRQ_RESERVED_13 13U +#define MRQ_RESERVED_14 14U +#define MRQ_RESERVED_15 15U +#define MRQ_RESERVED_16 16U +#define MRQ_RESERVED_17 17U +#define MRQ_RESERVED_18 18U +#define MRQ_RESERVED_24 24U +#define MRQ_RESERVED_25 25U +#define MRQ_RESERVED_26 26U +#define MRQ_RESERVED_30 30U +#define MRQ_RESERVED_64 64U +#define MRQ_RESERVED_74 74U +/** @endcond DEPRECATED */ /** @} */ @@ -167,7 +374,7 @@ struct mrq_response { * @brief Maximum MRQ code to be sent by CPU software to * BPMP. Subject to change in future */ -#define MAX_CPU_MRQ_ID 75U +#define MAX_CPU_MRQ_ID 84U /** * @addtogroup MRQ_Payloads @@ -183,8 +390,11 @@ struct mrq_response { * @defgroup ABI_info ABI Info * @defgroup Powergating Power Gating * @defgroup Thermal Thermal + * @defgroup OC_status OC status * @defgroup Vhint CPU Voltage hint * @defgroup EMC EMC + * @defgroup BWMGR BWMGR + * @defgroup ISO_CLIENT ISO_CLIENT * @defgroup CPU NDIV Limits * @defgroup RingbufConsole Ring Buffer Console * @defgroup Strap Straps @@ -192,8 +402,11 @@ struct mrq_response { * @defgroup CC3 Auto-CC3 * @defgroup FMON FMON * @defgroup EC EC - * @defgroup Fbvolt_status Fuse Burn Voltage Status - * @} + * @defgroup Telemetry Telemetry + * @defgroup Pwrlimit PWR_LIMIT + * @defgroup Gears Gears + * @defgroup BWMGR_INT Bandwidth Manager Integrated + * @} MRQ_Payloads */ /** @@ -304,190 +517,6 @@ struct mrq_query_fw_tag_response { uint8_t tag[32]; } BPMP_ABI_PACKED; -/** - * @ingroup MRQ_Codes - * @def MRQ_MODULE_LOAD - * @brief Dynamically load a BPMP code module - * - * * Platforms: T210, T210B01, T186 - * @cond (bpmp_t210 || bpmp_t210b01 || bpmp_t186) - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_module_load_request - * * Response Payload: @ref mrq_module_load_response - * - * @note This MRQ is disabled on production systems - * - */ - -/** - * @ingroup Module - * @brief Request with #MRQ_MODULE_LOAD - * - * Used by #MRQ_MODULE_LOAD calls to ask the recipient to dynamically - * load the code located at #phys_addr and having size #size - * bytes. #phys_addr is treated as a void pointer. - * - * The recipient copies the code from #phys_addr to locally allocated - * memory prior to responding to this message. - * - * @todo document the module header format - * - * The sender is responsible for ensuring that the code is mapped in - * the recipient's address map. - * - */ -struct mrq_module_load_request { - /** @brief Base address of the code to load */ - uint32_t phys_addr; - /** @brief Size in bytes of code to load */ - uint32_t size; -} BPMP_ABI_PACKED; - -/** - * @ingroup Module - * @brief Response to #MRQ_MODULE_LOAD - * - * @todo document mrq_response::err - */ -struct mrq_module_load_response { - /** @brief Handle to the loaded module */ - uint32_t base; -} BPMP_ABI_PACKED; -/** @endcond*/ - -/** - * @ingroup MRQ_Codes - * @def MRQ_MODULE_UNLOAD - * @brief Unload a previously loaded code module - * - * * Platforms: T210, T210B01, T186 - * @cond (bpmp_t210 || bpmp_t210b01 || bpmp_t186) - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_module_unload_request - * * Response Payload: N/A - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Module - * @brief Request with #MRQ_MODULE_UNLOAD - * - * Used by #MRQ_MODULE_UNLOAD calls to request that a previously loaded - * module be unloaded. - */ -struct mrq_module_unload_request { - /** @brief Handle of the module to unload */ - uint32_t base; -} BPMP_ABI_PACKED; -/** @endcond*/ - -/** - * @ingroup MRQ_Codes - * @def MRQ_TRACE_MODIFY - * @brief Modify the set of enabled trace events - * - * @deprecated - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_trace_modify_request - * * Response Payload: @ref mrq_trace_modify_response - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Trace - * @brief Request with #MRQ_TRACE_MODIFY - * - * Used by %MRQ_TRACE_MODIFY calls to enable or disable specify trace - * events. #set takes precedence for any bit set in both #set and - * #clr. - */ -struct mrq_trace_modify_request { - /** @brief Bit mask of trace events to disable */ - uint32_t clr; - /** @brief Bit mask of trace events to enable */ - uint32_t set; -} BPMP_ABI_PACKED; - -/** - * @ingroup Trace - * @brief Response to #MRQ_TRACE_MODIFY - * - * Sent in repsonse to an #MRQ_TRACE_MODIFY message. #mask reflects the - * state of which events are enabled after the recipient acted on the - * message. - * - */ -struct mrq_trace_modify_response { - /** @brief Bit mask of trace event enable states */ - uint32_t mask; -} BPMP_ABI_PACKED; - -/** - * @ingroup MRQ_Codes - * @def MRQ_WRITE_TRACE - * @brief Write trace data to a buffer - * - * @deprecated - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: @ref mrq_write_trace_request - * * Response Payload: @ref mrq_write_trace_response - * - * mrq_response::err depends on the @ref mrq_write_trace_request field - * values. err is -#BPMP_EINVAL if size is zero or area is NULL or - * area is in an illegal range. A positive value for err indicates the - * number of bytes written to area. - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Trace - * @brief Request with #MRQ_WRITE_TRACE - * - * Used by MRQ_WRITE_TRACE calls to ask the recipient to copy trace - * data from the recipient's local buffer to the output buffer. #area - * is treated as a byte-aligned pointer in the recipient's address - * space. - * - * The sender is responsible for ensuring that the output - * buffer is mapped in the recipient's address map. The recipient is - * responsible for protecting its own code and data from accidental - * overwrites. - */ -struct mrq_write_trace_request { - /** @brief Base address of output buffer */ - uint32_t area; - /** @brief Size in bytes of the output buffer */ - uint32_t size; -} BPMP_ABI_PACKED; - -/** - * @ingroup Trace - * @brief Response to #MRQ_WRITE_TRACE - * - * Once this response is sent, the respondent will not access the - * output buffer further. - */ -struct mrq_write_trace_response { - /** - * @brief Flag whether more data remains in local buffer - * - * Value is 1 if the entire local trace buffer has been - * drained to the outputbuffer. Value is 0 otherwise. - */ - uint32_t eof; -} BPMP_ABI_PACKED; - /** @private */ struct mrq_threaded_ping_request { uint32_t challenge; @@ -500,50 +529,6 @@ struct mrq_threaded_ping_response { /** * @ingroup MRQ_Codes - * @def MRQ_MODULE_MAIL - * @brief Send a message to a loadable module - * - * * Platforms: T210, T210B01, T186 - * @cond (bpmp_t210 || bpmp_t210b01 || bpmp_t186) - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_module_mail_request - * * Response Payload: @ref mrq_module_mail_response - * - * @note This MRQ is disabled on production systems - */ - -/** - * @ingroup Module - * @brief Request with #MRQ_MODULE_MAIL - */ -struct mrq_module_mail_request { - /** @brief Handle to the previously loaded module */ - uint32_t base; - /** @brief Module-specific mail payload - * - * The length of data[ ] is unknown to the BPMP core firmware - * but it is limited to the size of an IPC message. - */ - uint8_t data[BPMP_ABI_EMPTY_ARRAY]; -} BPMP_ABI_PACKED; - -/** - * @ingroup Module - * @brief Response to #MRQ_MODULE_MAIL - */ -struct mrq_module_mail_response { - /** @brief Module-specific mail payload - * - * The length of data[ ] is unknown to the BPMP core firmware - * but it is limited to the size of an IPC message. - */ - uint8_t data[BPMP_ABI_EMPTY_ARRAY]; -} BPMP_ABI_PACKED; -/** @endcond */ - -/** - * @ingroup MRQ_Codes * @def MRQ_DEBUGFS * @brief Interact with BPMP's debugfs file nodes * @@ -686,7 +671,7 @@ struct mrq_debugfs_response { #define DEBUGFS_S_ISDIR (1 << 9) #define DEBUGFS_S_IRUSR (1 << 8) #define DEBUGFS_S_IWUSR (1 << 7) -/** @} */ +/** @} Debugfs */ /** * @ingroup MRQ_Codes @@ -931,7 +916,7 @@ enum mrq_reset_commands { * @brief Request with MRQ_RESET * * Used by the sender of an #MRQ_RESET message to request BPMP to - * assert or deassert a given reset line. + * assert or or deassert a given reset line. */ struct mrq_reset_request { /** @brief Reset action to perform (@ref mrq_reset_commands) */ @@ -970,7 +955,7 @@ struct mrq_reset_response { } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ +/** @} Reset */ /** * @ingroup MRQ_Codes @@ -1032,7 +1017,17 @@ struct serial_i2c_request { * @brief Trigger one or more i2c transactions */ struct cmd_i2c_xfer_request { - /** @brief Valid bus number from @ref bpmp_i2c_ids*/ + /** + * @brief Tegra PWR_I2C bus identifier + * + * @cond (bpmp_t234 || bpmp_t239 || bpmp_t194) + * Must be set to 5. + * @endcond (bpmp_t234 || bpmp_t239 || bpmp_t194) + * @cond bpmp_th500 + * Must be set to 1. + * @endcond bpmp_th500 + * + */ uint32_t bus_id; /** @brief Count of valid bytes in #data_buf*/ @@ -1084,7 +1079,7 @@ struct mrq_i2c_response { struct cmd_i2c_xfer_response xfer; } BPMP_ABI_PACKED; -/** @} */ +/** @} I2C */ /** * @ingroup MRQ_Codes @@ -1109,6 +1104,13 @@ enum { CMD_CLK_IS_ENABLED = 6, CMD_CLK_ENABLE = 7, CMD_CLK_DISABLE = 8, +/** @cond DEPRECATED */ + CMD_CLK_PROPERTIES = 9, + CMD_CLK_POSSIBLE_PARENTS = 10, + CMD_CLK_NUM_POSSIBLE_PARENTS = 11, + CMD_CLK_GET_POSSIBLE_PARENT = 12, + CMD_CLK_RESET_REFCOUNTS = 13, +/** @endcond DEPRECATED */ CMD_CLK_GET_ALL_INFO = 14, CMD_CLK_GET_MAX_CLK_ID = 15, CMD_CLK_GET_FMAX_AT_VMIN = 16, @@ -1119,6 +1121,21 @@ enum { #define BPMP_CLK_HAS_SET_RATE (1U << 1U) #define BPMP_CLK_IS_ROOT (1U << 2U) #define BPMP_CLK_IS_VAR_ROOT (1U << 3U) +/** + * @brief Protection against rate and parent changes + * + * #MRQ_CLK command #CMD_CLK_SET_RATE or #MRQ_CLK command #CMD_CLK_SET_PARENT will return + * -#BPMP_EACCES. + */ +#define BPMP_CLK_RATE_PARENT_CHANGE_DENIED (1U << 30) + +/** + * @brief Protection against state changes + * + * #MRQ_CLK command #CMD_CLK_ENABLE or #MRQ_CLK command #CMD_CLK_DISABLE will return + * -#BPMP_EACCES. + */ +#define BPMP_CLK_STATE_CHANGE_DENIED (1U << 31) #define MRQ_CLK_NAME_MAXLEN 40U #define MRQ_CLK_MAX_PARENTS 16U @@ -1210,6 +1227,46 @@ struct cmd_clk_disable_response { BPMP_ABI_EMPTY } BPMP_ABI_PACKED; +/** @cond DEPRECATED */ +/** @private */ +struct cmd_clk_properties_request { + BPMP_ABI_EMPTY +} BPMP_ABI_PACKED; + +/** @todo flags need to be spelled out here */ +struct cmd_clk_properties_response { + uint32_t flags; +} BPMP_ABI_PACKED; + +/** @private */ +struct cmd_clk_possible_parents_request { + BPMP_ABI_EMPTY +} BPMP_ABI_PACKED; + +struct cmd_clk_possible_parents_response { + uint8_t num_parents; + uint8_t reserved[3]; + uint32_t parent_id[MRQ_CLK_MAX_PARENTS]; +} BPMP_ABI_PACKED; + +/** @private */ +struct cmd_clk_num_possible_parents_request { + BPMP_ABI_EMPTY +} BPMP_ABI_PACKED; + +struct cmd_clk_num_possible_parents_response { + uint8_t num_parents; +} BPMP_ABI_PACKED; + +struct cmd_clk_get_possible_parent_request { + uint8_t parent_idx; +} BPMP_ABI_PACKED; + +struct cmd_clk_get_possible_parent_response { + uint32_t parent_id; +} BPMP_ABI_PACKED; +/** @endcond DEPRECATED */ + /** @private */ struct cmd_clk_get_all_info_request { BPMP_ABI_EMPTY @@ -1241,6 +1298,7 @@ struct cmd_clk_get_fmax_at_vmin_response { int64_t rate; } BPMP_ABI_PACKED; + /** * @ingroup Clocks * @brief Request with #MRQ_CLK @@ -1267,6 +1325,17 @@ struct cmd_clk_get_fmax_at_vmin_response { * */ +/** @cond DEPRECATED + * + * Older versions of firmware also supported following sub-commands: + * |CMD_CLK_PROPERTIES |- | + * |CMD_CLK_POSSIBLE_PARENTS |- | + * |CMD_CLK_NUM_POSSIBLE_PARENTS|- | + * |CMD_CLK_GET_POSSIBLE_PARENT |clk_get_possible_parent| + * |CMD_CLK_RESET_REFCOUNTS |- | + * + * @endcond DEPRECATED */ + struct mrq_clk_request { /** @brief Sub-command and clock id concatenated to 32-bit word. * - bits[31..24] is the sub-cmd. @@ -1288,6 +1357,15 @@ struct mrq_clk_request { struct cmd_clk_disable_request clk_disable; /** @private */ struct cmd_clk_is_enabled_request clk_is_enabled; + /** @cond DEPRECATED */ + /** @private */ + struct cmd_clk_properties_request clk_properties; + /** @private */ + struct cmd_clk_possible_parents_request clk_possible_parents; + /** @private */ + struct cmd_clk_num_possible_parents_request clk_num_possible_parents; + struct cmd_clk_get_possible_parent_request clk_get_possible_parent; + /** @endcond DEPRECATED */ /** @private */ struct cmd_clk_get_all_info_request clk_get_all_info; /** @private */ @@ -1321,6 +1399,17 @@ struct mrq_clk_request { * */ +/** @cond DEPRECATED + * + * Older versions of firmware also supported following sub-commands: + * |CMD_CLK_PROPERTIES |clk_properties | + * |CMD_CLK_POSSIBLE_PARENTS |clk_possible_parents | + * |CMD_CLK_NUM_POSSIBLE_PARENTS|clk_num_possible_parents| + * |CMD_CLK_GET_POSSIBLE_PARENT |clk_get_possible_parents| + * |CMD_CLK_RESET_REFCOUNTS |- | + * + * @endcond DEPRECATED */ + struct mrq_clk_response { union { struct cmd_clk_get_rate_response clk_get_rate; @@ -1333,13 +1422,19 @@ struct mrq_clk_response { /** @private */ struct cmd_clk_disable_response clk_disable; struct cmd_clk_is_enabled_response clk_is_enabled; + /** @cond DEPRECATED */ + struct cmd_clk_properties_response clk_properties; + struct cmd_clk_possible_parents_response clk_possible_parents; + struct cmd_clk_num_possible_parents_response clk_num_possible_parents; + struct cmd_clk_get_possible_parent_response clk_get_possible_parent; + /** @endcond DEPRECATED */ struct cmd_clk_get_all_info_response clk_get_all_info; struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id; struct cmd_clk_get_fmax_at_vmin_response clk_get_fmax_at_vmin; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ +/** @} Clocks */ /** * @ingroup MRQ_Codes @@ -1378,107 +1473,20 @@ struct mrq_query_abi_response { } BPMP_ABI_PACKED; /** - * @ingroup MRQ_Codes - * @def MRQ_PG_READ_STATE - * @brief Read the power-gating state of a partition * - * * Platforms: T186 - * @cond bpmp_t186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_pg_read_state_request - * * Response Payload: @ref mrq_pg_read_state_response - */ - -/** - * @ingroup Powergating - * @brief Request with #MRQ_PG_READ_STATE - * - * Used by MRQ_PG_READ_STATE call to read the current state of a - * partition. - */ -struct mrq_pg_read_state_request { - /** @brief ID of partition */ - uint32_t partition_id; -} BPMP_ABI_PACKED; - -/** - * @ingroup Powergating - * @brief Response to MRQ_PG_READ_STATE - * @todo define possible errors. - */ -struct mrq_pg_read_state_response { - /** @brief Read as don't care */ - uint32_t sram_state; - /** @brief State of power partition - * * 0 : off - * * 1 : on - */ - uint32_t logic_state; -} BPMP_ABI_PACKED; -/** @endcond*/ -/** @} */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_PG_UPDATE_STATE - * @brief Modify the power-gating state of a partition. In contrast to - * MRQ_PG calls, the operations that change state (on/off) of power - * partition are reference counted. - * - * * Platforms: T186 - * @cond bpmp_t186 - * * Initiators: Any - * * Targets: BPMP - * * Request Payload: @ref mrq_pg_update_state_request - * * Response Payload: N/A - */ - -/** - * @ingroup Powergating - * @brief Request with mrq_pg_update_state_request - * - * Used by #MRQ_PG_UPDATE_STATE call to request BPMP to change the - * state of a power partition #partition_id. - */ -struct mrq_pg_update_state_request { - /** @brief ID of partition */ - uint32_t partition_id; - /** @brief Secondary control of power partition - * @details Ignored by many versions of the BPMP - * firmware. For maximum compatibility, set the value - * according to @ref logic_state - * * 0x1: power ON partition (@ref logic_state == 0x3) - * * 0x3: power OFF partition (@ref logic_state == 0x1) - */ - uint32_t sram_state; - /** @brief Controls state of power partition, legal values are - * * 0x1 : power OFF partition - * * 0x3 : power ON partition - */ - uint32_t logic_state; - /** @brief Change state of clocks of the power partition, legal values - * * 0x0 : do not change clock state - * * 0x1 : disable partition clocks (only applicable when - * @ref logic_state == 0x1) - * * 0x3 : enable partition clocks (only applicable when - * @ref logic_state == 0x3) - */ - uint32_t clock_state; -} BPMP_ABI_PACKED; -/** @endcond*/ - -/** * @ingroup MRQ_Codes * @def MRQ_PG * @brief Control power-gating state of a partition. In contrast to * MRQ_PG_UPDATE_STATE, operations that change the power partition * state are NOT reference counted * - * @note BPMP-FW forcefully turns off some partitions as part of SC7 entry - * because their state cannot be adequately restored on exit. Therefore, - * it is recommended to power off all domains via MRQ_PG prior to SC7 entry. + * @cond (bpmp_t194 || bpmp_t186) + * @note On T194 and earlier BPMP-FW forcefully turns off some partitions as + * part of SC7 entry because their state cannot be adequately restored on exit. + * Therefore, it is recommended to power off all domains via MRQ_PG prior to SC7 + * entry. * See @ref bpmp_pdomain_ids for further detail. + * @endcond (bpmp_t194 || bpmp_t186) * * * Platforms: T186, T194 * * Initiators: Any @@ -1643,7 +1651,7 @@ struct mrq_pg_response { } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ +/** @} Powergating */ /** * @ingroup MRQ_Codes @@ -1889,7 +1897,44 @@ union mrq_thermal_bpmp_to_host_response { struct cmd_thermal_get_thermtrip_response get_thermtrip; struct cmd_thermal_get_num_zones_response get_num_zones; } BPMP_ABI_PACKED; -/** @} */ + +/** @} Thermal */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_OC_STATUS + * @brief Query over current status + * + * * Platforms: T234 + * @cond bpmp_t234 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_oc_status_response + * + * @addtogroup OC_status + * @{ + */ + +#define OC_STATUS_MAX_SIZE 24U + +/* + * @brief Response to #MRQ_OC_STATUS + * + * throt_en: Value for each OC alarm where zero signifies throttle is + * disabled, and non-zero throttle is enabled. + * event_cnt: Total number of OC events for each OC alarm. + * + * mrq_response::err is 0 if the operation was successful and + * -#BPMP_ENODEV otherwise. + */ +struct mrq_oc_status_response { + uint8_t throt_en[OC_STATUS_MAX_SIZE]; + uint32_t event_cnt[OC_STATUS_MAX_SIZE]; +} BPMP_ABI_PACKED; + +/** @} OC_status */ +/** @endcond bpmp_t234 */ /** * @ingroup MRQ_Codes @@ -1948,8 +1993,9 @@ struct cpu_vhint_data { /** reserved for future use */ uint16_t reserved[328]; } BPMP_ABI_PACKED; -/** @endcond */ -/** @} */ + +/** @} Vhint */ +/** @endcond bpmp_t186 */ /** * @ingroup MRQ_Codes @@ -2016,14 +2062,15 @@ struct mrq_abi_ratchet_response { /** @brief BPMP's ratchet value */ uint16_t ratchet; }; -/** @} */ + +/** @} ABI_info */ /** * @ingroup MRQ_Codes * @def MRQ_EMC_DVFS_LATENCY * @brief Query frequency dependent EMC DVFS latency * - * * Platforms: T186, T194 + * * Platforms: T186, T194, T234 * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: N/A @@ -2053,7 +2100,543 @@ struct mrq_emc_dvfs_latency_response { struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE]; } BPMP_ABI_PACKED; -/** @} */ +/** @} EMC */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_EMC_DVFS_EMCHUB + * @brief Query EMC HUB frequencies + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_emc_dvfs_emchub_response + * @addtogroup EMC + * @{ + */ + +/** + * @brief Used by @ref mrq_emc_dvfs_emchub_response + */ +struct emc_dvfs_emchub { + /** @brief EMC DVFS node frequency in kHz */ + uint32_t freq; + /** @brief EMC HUB frequency in kHz */ + uint32_t hub_freq; +} BPMP_ABI_PACKED; + +#define EMC_DVFS_EMCHUB_MAX_SIZE EMC_DVFS_LATENCY_MAX_SIZE +/** + * @brief Response to #MRQ_EMC_DVFS_EMCHUB + */ +struct mrq_emc_dvfs_emchub_response { + /** @brief The number valid entries in #pairs */ + uint32_t num_pairs; + /** @brief EMC DVFS node <frequency, hub frequency> information */ + struct emc_dvfs_emchub pairs[EMC_DVFS_EMCHUB_MAX_SIZE]; +} BPMP_ABI_PACKED; + +/** @} EMC */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_EMC_DISP_RFL + * @brief Set EMC display RFL handshake mode of operations + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_emc_disp_rfl_request + * * Response Payload: N/A + * + * @addtogroup EMC + * @{ + */ + +enum mrq_emc_disp_rfl_mode { + /** @brief EMC display RFL handshake disabled */ + EMC_DISP_RFL_MODE_DISABLED = 0, + /** @brief EMC display RFL handshake enabled */ + EMC_DISP_RFL_MODE_ENABLED = 1, +}; + +/** + * @ingroup EMC + * @brief Request with #MRQ_EMC_DISP_RFL + * + * Used by the sender of an #MRQ_EMC_DISP_RFL message to + * request the mode of EMC display RFL handshake. + * + * mrq_response::err is + * * 0: RFL mode is set successfully + * * -#BPMP_EINVAL: invalid mode requested + * * -#BPMP_ENOSYS: RFL handshake is not supported + * * -#BPMP_EACCES: Permission denied + * * -#BPMP_ENODEV: if disp rfl mrq is not supported by BPMP-FW + */ +struct mrq_emc_disp_rfl_request { + /** @brief EMC display RFL mode (@ref mrq_emc_disp_rfl_mode) */ + uint32_t mode; +} BPMP_ABI_PACKED; + +/** @} EMC */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_BWMGR + * @brief bwmgr requests + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_bwmgr_request + * * Response Payload: @ref mrq_bwmgr_response + * + * @addtogroup BWMGR + * + * @{ + */ + +enum mrq_bwmgr_cmd { + /** + * @brief Check whether the BPMP driver supports the specified + * request type + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_BWMGR_QUERY_ABI = 0, + + /** + * @brief Determine dram rate to satisfy iso/niso bw requests + * + * mrq_response::err is + * * 0: calc_rate succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_ENOTSUP: Requested bw is not available. + */ + CMD_BWMGR_CALC_RATE = 1 +}; + +/* + * request data for request type CMD_BWMGR_QUERY_ABI + * + * type: Request type for which to check existence. + */ +struct cmd_bwmgr_query_abi_request { + uint32_t type; +} BPMP_ABI_PACKED; + +/** + * @brief Used by @ref cmd_bwmgr_calc_rate_request + */ +struct iso_req { + /* @brief bwmgr client ID @ref bpmp_bwmgr_ids */ + uint32_t id; + /* @brief bw in kBps requested by client */ + uint32_t iso_bw; +} BPMP_ABI_PACKED; + +#define MAX_ISO_CLIENTS 13U +/* + * request data for request type CMD_BWMGR_CALC_RATE + */ +struct cmd_bwmgr_calc_rate_request { + /* @brief total bw in kBps requested by all niso clients */ + uint32_t sum_niso_bw; + /* @brief The number of iso clients */ + uint32_t num_iso_clients; + /* @brief iso_req <id, iso_bw> information */ + struct iso_req isobw_reqs[MAX_ISO_CLIENTS]; +} BPMP_ABI_PACKED; + +/* + * response data for request type CMD_BWMGR_CALC_RATE + * + * iso_rate_min: min dram data clk rate in kHz to satisfy all iso bw reqs + * total_rate_min: min dram data clk rate in kHz to satisfy all bw reqs + */ +struct cmd_bwmgr_calc_rate_response { + uint32_t iso_rate_min; + uint32_t total_rate_min; +} BPMP_ABI_PACKED; + +/* + * @brief Request with #MRQ_BWMGR + * + * + * |sub-command |payload | + * |----------------------------|------------------------------| + * |CMD_BWMGR_QUERY_ABI | cmd_bwmgr_query_abi_request | + * |CMD_BWMGR_CALC_RATE | cmd_bwmgr_calc_rate_request | + * + */ +struct mrq_bwmgr_request { + uint32_t cmd; + union { + struct cmd_bwmgr_query_abi_request query_abi; + struct cmd_bwmgr_calc_rate_request bwmgr_rate_req; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/* + * @brief Response to MRQ_BWMGR + * + * |sub-command |payload | + * |----------------------------|------------------------------| + * |CMD_BWMGR_CALC_RATE | cmd_bwmgr_calc_rate_response | + */ +struct mrq_bwmgr_response { + union { + struct cmd_bwmgr_calc_rate_response bwmgr_rate_resp; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** @} BWMGR */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_BWMGR_INT + * @brief bpmp-integrated bwmgr requests + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_bwmgr_int_request + * * Response Payload: @ref mrq_bwmgr_int_response + * + * @addtogroup BWMGR_INT + * @{ + */ + +enum mrq_bwmgr_int_cmd { + /** + * @brief Check whether the BPMP-FW supports the specified + * request type + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_BWMGR_INT_QUERY_ABI = 1, + + /** + * @brief Determine and set dram rate to satisfy iso/niso bw request + * + * mrq_response::err is + * * 0: request succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * set_frequency in @ref cmd_bwmgr_int_calc_and_set_response + * will not be set. + * * -#BPMP_ENOTSUP: Requested bw is not available. + * set_frequency in @ref cmd_bwmgr_int_calc_and_set_response + * will be current dram-clk rate. + */ + CMD_BWMGR_INT_CALC_AND_SET = 2, + + /** + * @brief Set a max DRAM frequency for the bandwidth-manager + * + * mrq_response::err is + * * 0: request succeeded. + * * -#BPMP_ENOTSUP: Requested cap frequency is not possible. + */ + CMD_BWMGR_INT_CAP_SET = 3 +}; + +/* + * request structure for request type CMD_BWMGR_QUERY_ABI + * + * type: Request type for which to check existence. + */ +struct cmd_bwmgr_int_query_abi_request { + /* @brief request type determined by @ref mrq_bwmgr_int_cmd */ + uint32_t type; +} BPMP_ABI_PACKED; + +/** + * @defgroup bwmgr_int_unit_type BWMGR_INT floor unit-types + * @addtogroup bwmgr_int_unit_type + * @{ + */ +/** @brief kilobytes per second unit-type */ +#define BWMGR_INT_UNIT_KBPS 0U +/** @brief kilohertz unit-type */ +#define BWMGR_INT_UNIT_KHZ 1U + +/** @} bwmgr_int_unit_type */ + +/* + * request data for request type CMD_BWMGR_INT_CALC_AND_SET + */ +struct cmd_bwmgr_int_calc_and_set_request { + /* @brief bwmgr client ID @ref bpmp_bwmgr_ids */ + uint32_t client_id; + /* @brief average niso bw usage in kBps requested by client. */ + uint32_t niso_bw; + /* + * @brief average iso bw usage in kBps requested by client. + * Value is ignored if client is niso. Determined by client_id. + */ + uint32_t iso_bw; + /* + * @brief memory clock floor requested by client. + * Unit determined by floor_unit. + */ + uint32_t mc_floor; + /* + * @brief toggle to determine the unit-type of floor value. + * See @ref bwmgr_int_unit_type definitions for unit-type mappings. + */ + uint8_t floor_unit; +} BPMP_ABI_PACKED; + +struct cmd_bwmgr_int_cap_set_request { + /* @brief requested cap frequency in Hz. */ + uint64_t rate; +} BPMP_ABI_PACKED; + +/* + * response data for request type CMD_BWMGR_CALC_AND_SET + */ +struct cmd_bwmgr_int_calc_and_set_response { + /* @brief current set memory clock frequency in Hz */ + uint64_t rate; +} BPMP_ABI_PACKED; + +/* + * @brief Request with #MRQ_BWMGR_INT + * + * + * |sub-command |payload | + * |----------------------------|-----------------------------------| + * |CMD_BWMGR_INT_QUERY_ABI | cmd_bwmgr_int_query_abi_request | + * |CMD_BWMGR_INT_CALC_AND_SET | cmd_bwmgr_int_calc_and_set_request| + * |CMD_BWMGR_INT_CAP_SET | cmd_bwmgr_int_cap_set_request | + * + */ +struct mrq_bwmgr_int_request { + uint32_t cmd; + union { + struct cmd_bwmgr_int_query_abi_request query_abi; + struct cmd_bwmgr_int_calc_and_set_request bwmgr_calc_set_req; + struct cmd_bwmgr_int_cap_set_request bwmgr_cap_set_req; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/* + * @brief Response to MRQ_BWMGR_INT + * + * |sub-command |payload | + * |----------------------------|---------------------------------------| + * |CMD_BWMGR_INT_CALC_AND_SET | cmd_bwmgr_int_calc_and_set_response | + */ +struct mrq_bwmgr_int_response { + union { + struct cmd_bwmgr_int_calc_and_set_response bwmgr_calc_set_resp; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** @} BWMGR_INT */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_ISO_CLIENT + * @brief ISO client requests + * + * * Platforms: T234 onwards + * @cond (bpmp_t234 || bpmp_t239 || bpmp_th500) + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_iso_client_request + * * Response Payload: @ref mrq_iso_client_response + * + * @addtogroup ISO_CLIENT + * @{ + */ + +enum mrq_iso_client_cmd { + /** + * @brief Check whether the BPMP driver supports the specified + * request type + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_ISO_CLIENT_QUERY_ABI = 0, + + /* + * @brief check for legal LA for the iso client. Without programming + * LA MC registers, calculate and ensure that legal LA is possible for + * iso bw requested by the ISO client. + * + * mrq_response::err is + * * 0: check la succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_EFAULT: Legal LA is not possible for client requested iso_bw + */ + CMD_ISO_CLIENT_CALCULATE_LA = 1, + + /* + * @brief set LA for the iso client. Calculate and program the LA/PTSA + * MC registers corresponding to the client making bw request + * + * mrq_response::err is + * * 0: set la succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_EFAULT: Failed to calculate or program MC registers. + */ + CMD_ISO_CLIENT_SET_LA = 2, + + /* + * @brief Get max possible bw for iso client + * + * mrq_response::err is + * * 0: get_max_bw succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + */ + CMD_ISO_CLIENT_GET_MAX_BW = 3 +}; + +/* + * request data for request type CMD_ISO_CLIENT_QUERY_ABI + * + * type: Request type for which to check existence. + */ +struct cmd_iso_client_query_abi_request { + uint32_t type; +} BPMP_ABI_PACKED; + +/* + * request data for request type CMD_ISO_CLIENT_CALCULATE_LA + * + * id: client ID in @ref bpmp_bwmgr_ids + * bw: bw requested in kBps by client ID. + * init_bw_floor: initial dram_bw_floor in kBps passed by client ID. + * ISO client will perform mempool allocation and DVFS buffering based + * on this dram_bw_floor. + */ +struct cmd_iso_client_calculate_la_request { + uint32_t id; + uint32_t bw; + uint32_t init_bw_floor; +} BPMP_ABI_PACKED; + +/* + * request data for request type CMD_ISO_CLIENT_SET_LA + * + * id: client ID in @ref bpmp_bwmgr_ids + * bw: bw requested in kBps by client ID. + * final_bw_floor: final dram_bw_floor in kBps. + * Sometimes the initial dram_bw_floor passed by ISO client may need to be + * updated by considering higher dram freq's. This is the final dram_bw_floor + * used to calculate and program MC registers. + */ +struct cmd_iso_client_set_la_request { + uint32_t id; + uint32_t bw; + uint32_t final_bw_floor; +} BPMP_ABI_PACKED; + +/* + * request data for request type CMD_ISO_CLIENT_GET_MAX_BW + * + * id: client ID in @ref bpmp_bwmgr_ids + */ +struct cmd_iso_client_get_max_bw_request { + uint32_t id; +} BPMP_ABI_PACKED; + +/* + * response data for request type CMD_ISO_CLIENT_CALCULATE_LA + * + * la_rate_floor: minimum dram_rate_floor in kHz at which a legal la is possible + * iso_client_only_rate: Minimum dram freq in kHz required to satisfy this clients + * iso bw request, assuming all other iso clients are inactive + */ +struct cmd_iso_client_calculate_la_response { + uint32_t la_rate_floor; + uint32_t iso_client_only_rate; +} BPMP_ABI_PACKED; + +/** + * @brief Used by @ref cmd_iso_client_get_max_bw_response + */ +struct iso_max_bw { + /* @brief dram frequency in kHz */ + uint32_t freq; + /* @brief max possible iso-bw in kBps */ + uint32_t iso_bw; +} BPMP_ABI_PACKED; + +#define ISO_MAX_BW_MAX_SIZE 14U +/* + * response data for request type CMD_ISO_CLIENT_GET_MAX_BW + */ +struct cmd_iso_client_get_max_bw_response { + /* @brief The number valid entries in iso_max_bw pairs */ + uint32_t num_pairs; + /* @brief max ISOBW <dram freq, max bw> information */ + struct iso_max_bw pairs[ISO_MAX_BW_MAX_SIZE]; +} BPMP_ABI_PACKED; + +/** + * @brief Request with #MRQ_ISO_CLIENT + * + * Used by the sender of an #MRQ_ISO_CLIENT message. + * + * |sub-command |payload | + * |------------------------------------ |----------------------------------------| + * |CMD_ISO_CLIENT_QUERY_ABI |cmd_iso_client_query_abi_request | + * |CMD_ISO_CLIENT_CALCULATE_LA |cmd_iso_client_calculate_la_request | + * |CMD_ISO_CLIENT_SET_LA |cmd_iso_client_set_la_request | + * |CMD_ISO_CLIENT_GET_MAX_BW |cmd_iso_client_get_max_bw_request | + * + */ + +struct mrq_iso_client_request { + /* Type of request. Values listed in enum mrq_iso_client_cmd */ + uint32_t cmd; + union { + struct cmd_iso_client_query_abi_request query_abi; + struct cmd_iso_client_calculate_la_request calculate_la_req; + struct cmd_iso_client_set_la_request set_la_req; + struct cmd_iso_client_get_max_bw_request max_isobw_req; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** + * @brief Response to MRQ_ISO_CLIENT + * + * Each sub-command supported by @ref mrq_iso_client_request may return + * sub-command-specific data. Some do and some do not as indicated in + * the following table + * + * |sub-command |payload | + * |---------------------------- |------------------------------------| + * |CMD_ISO_CLIENT_CALCULATE_LA |cmd_iso_client_calculate_la_response| + * |CMD_ISO_CLIENT_SET_LA |N/A | + * |CMD_ISO_CLIENT_GET_MAX_BW |cmd_iso_client_get_max_bw_response | + * + */ + +struct mrq_iso_client_response { + union { + struct cmd_iso_client_calculate_la_response calculate_la_resp; + struct cmd_iso_client_get_max_bw_response max_isobw_resp; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** @} ISO_CLIENT */ +/** @endcond (bpmp_t234 || bpmp_t239 || bpmp_th500) */ /** * @ingroup MRQ_Codes @@ -2061,7 +2644,7 @@ struct mrq_emc_dvfs_latency_response { * @brief CPU freq. limits in ndiv * * * Platforms: T194 onwards - * @cond bpmp_t194 + * @cond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_cpu_ndiv_limits_request @@ -2094,15 +2677,15 @@ struct mrq_cpu_ndiv_limits_response { uint16_t ndiv_min; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ +/** @} CPU */ +/** @endcond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) */ /** * @ingroup MRQ_Codes * @def MRQ_CPU_AUTO_CC3 * @brief Query CPU cluster auto-CC3 configuration * - * * Platforms: T194 onwards + * * Platforms: T194 * @cond bpmp_t194 * * Initiators: CCPLEX * * Targets: BPMP @@ -2140,40 +2723,8 @@ struct mrq_cpu_auto_cc3_response { uint32_t auto_cc3_config; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ - -/** - * @ingroup MRQ_Codes - * @def MRQ_TRACE_ITER - * @brief Manage the trace iterator - * - * @deprecated - * - * * Platforms: All - * * Initiators: CCPLEX - * * Targets: BPMP - * * Request Payload: N/A - * * Response Payload: @ref mrq_trace_iter_request - * @addtogroup Trace - * @{ - */ -enum { - /** @brief (re)start the tracing now. Ignore older events */ - TRACE_ITER_INIT = 0, - /** @brief Clobber all events in the trace buffer */ - TRACE_ITER_CLEAN = 1 -}; - -/** - * @brief Request with #MRQ_TRACE_ITER - */ -struct mrq_trace_iter_request { - /** @brief TRACE_ITER_INIT or TRACE_ITER_CLEAN */ - uint32_t cmd; -} BPMP_ABI_PACKED; - -/** @} */ +/** @} CC3 */ +/** @endcond bpmp_t194 */ /** * @ingroup MRQ_Codes @@ -2351,7 +2902,8 @@ union mrq_ringbuf_console_bpmp_to_host_response { struct cmd_ringbuf_console_write_resp write; struct cmd_ringbuf_console_get_fifo_resp get_fifo; } BPMP_ABI_PACKED; -/** @} */ + +/** @} RingbufConsole */ /** * @ingroup MRQ_Codes @@ -2359,7 +2911,7 @@ union mrq_ringbuf_console_bpmp_to_host_response { * @brief Set a strap value controlled by BPMP * * * Platforms: T194 onwards - * @cond bpmp_t194 + * @cond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_strap_request @@ -2390,17 +2942,14 @@ enum mrq_strap_cmd { struct mrq_strap_request { /** @brief @ref mrq_strap_cmd */ uint32_t cmd; - /** @brief Strap ID from @ref Strap_Ids */ + /** @brief Strap ID from @ref Strap_Identifiers */ uint32_t id; /** @brief Desired value for strap (if cmd is #STRAP_SET) */ uint32_t value; } BPMP_ABI_PACKED; -/** - * @defgroup Strap_Ids Strap Identifiers - * @} - */ -/** @endcond */ +/** @} Strap */ +/** @endcond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) */ /** * @ingroup MRQ_Codes @@ -2408,7 +2957,7 @@ struct mrq_strap_request { * @brief Perform a UPHY operation * * * Platforms: T194 onwards - * @cond bpmp_t194 + * @cond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_uphy_request @@ -2423,6 +2972,9 @@ enum { CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT = 3, CMD_UPHY_PCIE_CONTROLLER_STATE = 4, CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF = 5, + CMD_UPHY_DISPLAY_PORT_INIT = 6, + CMD_UPHY_DISPLAY_PORT_OFF = 7, + CMD_UPHY_XUSB_DYN_LANES_RESTORE = 8, CMD_UPHY_MAX, }; @@ -2445,28 +2997,41 @@ struct cmd_uphy_margin_status_response { } BPMP_ABI_PACKED; struct cmd_uphy_ep_controller_pll_init_request { - /** @brief EP controller number, valid: 0, 4, 5 */ + /** @brief EP controller number, T194 valid: 0, 4, 5; T234 valid: 5, 6, 7, 10; T239 valid: 0 */ uint8_t ep_controller; } BPMP_ABI_PACKED; struct cmd_uphy_pcie_controller_state_request { - /** @brief PCIE controller number, valid: 0, 1, 2, 3, 4 */ + /** @brief PCIE controller number, T194 valid: 0-4; T234 valid: 0-10; T239 valid: 0-3 */ uint8_t pcie_controller; uint8_t enable; } BPMP_ABI_PACKED; struct cmd_uphy_ep_controller_pll_off_request { - /** @brief EP controller number, valid: 0, 4, 5 */ + /** @brief EP controller number, T194 valid: 0, 4, 5; T234 valid: 5, 6, 7, 10; T239 valid: 0 */ uint8_t ep_controller; } BPMP_ABI_PACKED; +struct cmd_uphy_display_port_init_request { + /** @brief DisplayPort link rate, T239 valid: 1620, 2700, 5400, 8100, 2160, 2430, 3240, 4320, 6750 */ + uint16_t link_rate; + /** @brief 1: lane 0; 2: lane 1; 3: lane 0 and 1 */ + uint16_t lanes_bitmap; +} BPMP_ABI_PACKED; + +struct cmd_uphy_xusb_dyn_lanes_restore_request { + /** @brief 1: lane 0; 2: lane 1; 3: lane 0 and 1 */ + uint16_t lanes_bitmap; +} BPMP_ABI_PACKED; + /** * @ingroup UPHY * @brief Request with #MRQ_UPHY * - * Used by the sender of an #MRQ_UPHY message to control UPHY Lane RX margining. - * The uphy_request is split into several sub-commands. Some sub-commands - * require no additional data. Others have a sub-command specific payload + * Used by the sender of an #MRQ_UPHY message to control UPHY. + * The uphy_request is split into several sub-commands. CMD_UPHY_PCIE_LANE_MARGIN_STATUS + * requires no additional data. Others have a sub-command specific payload. Below table + * shows sub-commands with their corresponding payload data. * * |sub-command |payload | * |------------------------------------ |----------------------------------------| @@ -2475,6 +3040,9 @@ struct cmd_uphy_ep_controller_pll_off_request { * |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT |cmd_uphy_ep_controller_pll_init_request | * |CMD_UPHY_PCIE_CONTROLLER_STATE |cmd_uphy_pcie_controller_state_request | * |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF |cmd_uphy_ep_controller_pll_off_request | + * |CMD_UPHY_PCIE_DISPLAY_PORT_INIT |cmd_uphy_display_port_init_request | + * |CMD_UPHY_PCIE_DISPLAY_PORT_OFF | | + * |CMD_UPHY_XUSB_DYN_LANES_RESTORE |cmd_uphy_xusb_dyn_lanes_restore_request | * */ @@ -2489,6 +3057,8 @@ struct mrq_uphy_request { struct cmd_uphy_ep_controller_pll_init_request ep_ctrlr_pll_init; struct cmd_uphy_pcie_controller_state_request controller_state; struct cmd_uphy_ep_controller_pll_off_request ep_ctrlr_pll_off; + struct cmd_uphy_display_port_init_request display_port_init; + struct cmd_uphy_xusb_dyn_lanes_restore_request xusb_dyn_lanes_restore; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; @@ -2513,8 +3083,8 @@ struct mrq_uphy_response { } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ +/** @} UPHY */ +/** @endcond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) */ /** * @ingroup MRQ_Codes @@ -2522,14 +3092,16 @@ struct mrq_uphy_response { * @brief Perform a frequency monitor configuration operations * * * Platforms: T194 onwards - * @cond bpmp_t194 + * @cond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_fmon_request * * Response Payload: @ref mrq_fmon_response + * @endcond (bpmp_t194 || bpmp_t234 || bpmp_t239 || bpmp_th500) * * @addtogroup FMON * @{ + * @cond (bpmp_t194 || bpmp_t234) */ enum { /** @@ -2538,6 +3110,20 @@ enum { * The monitored clock must be running for clamp to succeed. If * clamped, FMON configuration is preserved when clock rate * and/or state is changed. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_EACCES: FMON access error @n + * -#BPMP_EBADCMD if subcommand is not supported @n + * -#BPMP_EBADSLT: clamp FMON on cluster with auto-CC3 enabled @n + * -#BPMP_EBUSY: fmon is already clamped at different rate @n + * -#BPMP_EFAULT: self-diagnostic error @n + * -#BPMP_EINVAL: invalid FMON configuration @n + * -#BPMP_EOPNOTSUPP: not in production mode @n + * -#BPMP_ENODEV: invalid clk_id @n + * -#BPMP_ENOENT: no calibration data, uninitialized @n + * -#BPMP_ENOTSUP: avfs config not set @n + * -#BPMP_ENOSYS: clamp FMON on cluster clock w/ no NAFLL @n + * -#BPMP_ETIMEDOUT: operation timed out @n */ CMD_FMON_GEAR_CLAMP = 1, /** @@ -2545,6 +3131,13 @@ enum { * * Allow FMON configuration to follow monitored clock rate * and/or state changes. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_EBADCMD if subcommand is not supported @n + * -#BPMP_ENODEV: invalid clk_id @n + * -#BPMP_ENOENT: no calibration data, uninitialized @n + * -#BPMP_ENOTSUP: avfs config not set @n + * -#BPMP_EOPNOTSUPP: not in production mode @n */ CMD_FMON_GEAR_FREE = 2, /** @@ -2553,11 +3146,54 @@ enum { * * Inherently racy, since clamp state can be changed * concurrently. Useful for testing. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_EBADCMD if subcommand is not supported @n + * -#BPMP_ENODEV: invalid clk_id @n + * -#BPMP_ENOENT: no calibration data, uninitialized @n + * -#BPMP_ENOTSUP: avfs config not set @n + * -#BPMP_EOPNOTSUPP: not in production mode @n */ CMD_FMON_GEAR_GET = 3, - CMD_FMON_NUM, + /** + * @brief Return current status of FMON faults detected by FMON + * h/w or s/w since last invocation of this command. + * Clears fault status. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_EBADCMD if subcommand is not supported @n + * -#BPMP_EINVAL: invalid fault type @n + * -#BPMP_ENODEV: invalid clk_id @n + * -#BPMP_ENOENT: no calibration data, uninitialized @n + * -#BPMP_ENOTSUP: avfs config not set @n + * -#BPMP_EOPNOTSUPP: not in production mode @n + */ + CMD_FMON_FAULT_STS_GET = 4, }; +/** + * @cond DEPRECATED + * Kept for backward compatibility + */ +#define CMD_FMON_NUM 4 + +/** @endcond DEPRECATED */ + +/** + * @defgroup fmon_fault_type FMON fault type + * @addtogroup fmon_fault_type + * @{ + */ +/** @brief All detected FMON faults (h/w or s/w) */ +#define FMON_FAULT_TYPE_ALL 0U +/** @brief FMON faults detected by h/w */ +#define FMON_FAULT_TYPE_HW 1U +/** @brief FMON faults detected by s/w */ +#define FMON_FAULT_TYPE_SW 2U + +/** @} fmon_fault_type */ + + struct cmd_fmon_gear_clamp_request { int32_t unused; int64_t rate; @@ -2587,6 +3223,14 @@ struct cmd_fmon_gear_get_response { int64_t rate; } BPMP_ABI_PACKED; +struct cmd_fmon_fault_sts_get_request { + uint32_t fault_type; /**< @ref fmon_fault_type */ +} BPMP_ABI_PACKED; + +struct cmd_fmon_fault_sts_get_response { + uint32_t fault_sts; +} BPMP_ABI_PACKED; + /** * @ingroup FMON * @brief Request with #MRQ_FMON @@ -2601,9 +3245,9 @@ struct cmd_fmon_gear_get_response { * |CMD_FMON_GEAR_CLAMP |fmon_gear_clamp | * |CMD_FMON_GEAR_FREE |- | * |CMD_FMON_GEAR_GET |- | + * |CMD_FMON_FAULT_STS_GET |fmon_fault_sts_get | * */ - struct mrq_fmon_request { /** @brief Sub-command and clock id concatenated to 32-bit word. * - bits[31..24] is the sub-cmd. @@ -2618,6 +3262,7 @@ struct mrq_fmon_request { struct cmd_fmon_gear_free_request fmon_gear_free; /** @private */ struct cmd_fmon_gear_get_request fmon_gear_get; + struct cmd_fmon_fault_sts_get_request fmon_fault_sts_get; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; @@ -2633,6 +3278,7 @@ struct mrq_fmon_request { * |CMD_FMON_GEAR_CLAMP |- | * |CMD_FMON_GEAR_FREE |- | * |CMD_FMON_GEAR_GET |fmon_gear_get | + * |CMD_FMON_FAULT_STS_GET |fmon_fault_sts_get | * */ @@ -2643,11 +3289,12 @@ struct mrq_fmon_response { /** @private */ struct cmd_fmon_gear_free_response fmon_gear_free; struct cmd_fmon_gear_get_response fmon_gear_get; + struct cmd_fmon_fault_sts_get_response fmon_fault_sts_get; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ +/** @endcond (bpmp_t194 || bpmp_t234) */ +/** @} FMON */ /** * @ingroup MRQ_Codes @@ -2655,7 +3302,7 @@ struct mrq_fmon_response { * @brief Provide status information on faults reported by Error * Collator (EC) to HSM. * - * * Platforms: T194 onwards + * * Platforms: T194 * @cond bpmp_t194 * * Initiators: CCPLEX * * Targets: BPMP @@ -2664,8 +3311,10 @@ struct mrq_fmon_response { * * @note This MRQ ABI is under construction, and subject to change * + * @endcond bpmp_t194 * @addtogroup EC * @{ + * @cond bpmp_t194 */ enum { /** @@ -2676,7 +3325,7 @@ enum { * -#BPMP_ENODEV if target EC is not owned by BPMP @n * -#BPMP_EACCES if target EC power domain is turned off @n * -#BPMP_EBADCMD if subcommand is not supported - * @endcond + * @endcond DEPRECATED */ CMD_EC_STATUS_GET = 1, /* deprecated */ @@ -2787,7 +3436,8 @@ enum ec_registers_group { #define EC_STATUS_FLAG_LAST_ERROR 0x0002U /** @brief EC latent error flag */ #define EC_STATUS_FLAG_LATENT_ERROR 0x0004U -/** @} */ + +/** @} bpmp_ec_status_flags */ /** * @defgroup bpmp_ec_desc_flags EC Descriptor Flags @@ -2798,7 +3448,8 @@ enum ec_registers_group { #define EC_DESC_FLAG_RESOLVED 0x0001U /** @brief EC descriptor failed to retrieve id flag */ #define EC_DESC_FLAG_NO_ID 0x0002U -/** @} */ + +/** @} bpmp_ec_desc_flags */ /** * |error type | fmon_clk_id values | @@ -2810,14 +3461,18 @@ struct ec_err_fmon_desc { uint16_t desc_flags; /** @brief FMON monitored clock id */ uint16_t fmon_clk_id; - /** @brief Bitmask of @ref bpmp_fmon_faults_flags */ + /** + * @brief Bitmask of fault flags + * + * @ref bpmp_fmon_faults_flags + */ uint32_t fmon_faults; /** @brief FMON faults access error */ int32_t fmon_access_error; } BPMP_ABI_PACKED; /** - * |error type | vmon_adc_id values | + * | error type | vmon_adc_id values | * |---------------------------------|---------------------------| * |@ref EC_ERR_TYPE_VOLTAGE_MONITOR |@ref bpmp_adc_ids | */ @@ -2826,16 +3481,16 @@ struct ec_err_vmon_desc { uint16_t desc_flags; /** @brief VMON rail adc id */ uint16_t vmon_adc_id; - /** @brief Bitmask of @ref bpmp_vmon_faults_flags */ + /** @brief Bitmask of bpmp_vmon_faults_flags */ uint32_t vmon_faults; /** @brief VMON faults access error */ int32_t vmon_access_error; } BPMP_ABI_PACKED; /** - * |error type | reg_id values | - * |---------------------------------|---------------------------| - * |@ref EC_ERR_TYPE_REGISTER_PARITY |@ref bpmp_ec_registers_ids | + * |error type | reg_id values | + * |---------------------------------|-----------------------| + * |@ref EC_ERR_TYPE_REGISTER_PARITY | bpmp_ec_registers_ids | */ struct ec_err_reg_parity_desc { /** @brief Bitmask of @ref bpmp_ec_desc_flags */ @@ -2847,10 +3502,10 @@ struct ec_err_reg_parity_desc { } BPMP_ABI_PACKED; /** - * |error type | err_source_id values | - * |--------------------------------- |--------------------------| - * |@ref EC_ERR_TYPE_SW_CORRECTABLE | @ref bpmp_ec_ce_swd_ids | - * |@ref EC_ERR_TYPE_SW_UNCORRECTABLE | @ref bpmp_ec_ue_swd_ids | + * |error type | err_source_id values | + * |--------------------------------- |----------------------| + * |@ref EC_ERR_TYPE_SW_CORRECTABLE | bpmp_ec_ce_swd_ids | + * |@ref EC_ERR_TYPE_SW_UNCORRECTABLE | bpmp_ec_ue_swd_ids | */ struct ec_err_sw_error_desc { /** @brief Bitmask of @ref bpmp_ec_desc_flags */ @@ -2862,15 +3517,15 @@ struct ec_err_sw_error_desc { } BPMP_ABI_PACKED; /** - * |error type | err_source_id values | - * |----------------------------------------|---------------------------| - * |@ref EC_ERR_TYPE_PARITY_INTERNAL |@ref bpmp_ec_ipath_ids | - * |@ref EC_ERR_TYPE_ECC_SEC_INTERNAL |@ref bpmp_ec_ipath_ids | - * |@ref EC_ERR_TYPE_ECC_DED_INTERNAL |@ref bpmp_ec_ipath_ids | - * |@ref EC_ERR_TYPE_COMPARATOR |@ref bpmp_ec_comparator_ids| - * |@ref EC_ERR_TYPE_PARITY_SRAM |@ref bpmp_clock_ids | - * |@ref EC_ERR_TYPE_OTHER_HW_CORRECTABLE |@ref bpmp_ec_misc_hwd_ids | - * |@ref EC_ERR_TYPE_OTHER_HW_UNCORRECTABLE |@ref bpmp_ec_misc_hwd_ids | + * |error type | err_source_id values | + * |----------------------------------------|------------------------| + * |@ref EC_ERR_TYPE_PARITY_INTERNAL | bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_ECC_SEC_INTERNAL | bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_ECC_DED_INTERNAL | bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_COMPARATOR | bpmp_ec_comparator_ids| + * |@ref EC_ERR_TYPE_OTHER_HW_CORRECTABLE | bpmp_ec_misc_hwd_ids | + * |@ref EC_ERR_TYPE_OTHER_HW_UNCORRECTABLE | bpmp_ec_misc_hwd_ids | + * |@ref EC_ERR_TYPE_PARITY_SRAM | bpmp_clock_ids | */ struct ec_err_simple_desc { /** @brief Bitmask of @ref bpmp_ec_desc_flags */ @@ -2917,7 +3572,7 @@ struct cmd_ec_status_get_response { /** @brief EC error descriptors */ union ec_err_desc error_descs[EC_ERR_STATUS_DESC_MAX_NUM]; } BPMP_ABI_PACKED; -/** @endcond */ +/** @endcond DEPRECATED */ struct cmd_ec_status_ex_get_response { /** @brief Target EC id (the same id received with request). */ @@ -2955,7 +3610,7 @@ struct cmd_ec_status_ex_get_response { * |sub-command |payload | * |----------------------------|-----------------------| * |@ref CMD_EC_STATUS_GET |ec_status_get | - * @endcond + * @endcond DEPRECATED * * |sub-command |payload | * |----------------------------|-----------------------| @@ -2983,7 +3638,7 @@ struct mrq_ec_request { * |sub-command |payload | * |----------------------------|------------------------| * |@ref CMD_EC_STATUS_GET |ec_status_get | - * @endcond + * @endcond DEPRECATED * * |sub-command |payload | * |----------------------------|------------------------| @@ -2997,13 +3652,264 @@ struct mrq_ec_response { * @cond DEPRECATED */ struct cmd_ec_status_get_response ec_status_get; - /** @endcond */ + /** @endcond DEPRECATED */ struct cmd_ec_status_ex_get_response ec_status_ex_get; } BPMP_UNION_ANON; } BPMP_ABI_PACKED; -/** @} */ -/** @endcond */ +/** @endcond bpmp_t194 */ +/** @} EC */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_TELEMETRY + * @brief Get address of memory buffer refreshed with recently sampled + * telemetry data + * + * * Platforms: TH500 onwards + * @cond bpmp_th500 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_telemetry_response + * @addtogroup Telemetry + * @{ + */ + +/** + * @brief Response to #MRQ_TELEMETRY + * + * mrq_response::err is + * * 0: Telemetry data is available at returned address + * * -#BPMP_EACCES: MRQ master is not allowed to request buffer refresh + * * -#BPMP_ENAVAIL: Telemetry buffer cannot be refreshed via this MRQ channel + * * -#BPMP_ENOTSUP: Telemetry buffer is not supported by BPMP-FW + * * -#BPMP_ENODEV: Telemetry mrq is not supported by BPMP-FW + */ +struct mrq_telemetry_response { + /** @brief Physical address of telemetry data buffer */ + uint64_t data_buf_addr; /**< see @ref bpmp_telemetry_layout */ +} BPMP_ABI_PACKED; + +/** @} Telemetry */ +/** @endcond bpmp_th500 */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_PWR_LIMIT + * @brief Control power limits. + * + * * Platforms: TH500 onwards + * @cond bpmp_th500 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_pwr_limit_request + * * Response Payload: @ref mrq_pwr_limit_response + * + * @addtogroup Pwrlimit + * @{ + */ +enum mrq_pwr_limit_cmd { + /** + * @brief Check whether the BPMP-FW supports the specified + * command + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_PWR_LIMIT_QUERY_ABI = 0, + + /** + * @brief Set power limit + * + * mrq_response:err is + * * 0: Success + * * -#BPMP_ENODEV: Pwr limit mrq is not supported by BPMP-FW + * * -#BPMP_ENAVAIL: Invalid request parameters + * * -#BPMP_EACCES: Request is not accepted + */ + CMD_PWR_LIMIT_SET = 1, + + /** + * @brief Get power limit setting + * + * mrq_response:err is + * * 0: Success + * * -#BPMP_ENODEV: Pwr limit mrq is not supported by BPMP-FW + * * -#BPMP_ENAVAIL: Invalid request parameters + */ + CMD_PWR_LIMIT_GET = 2, + + /** + * @brief Get current power cap + * + * mrq_response:err is + * * 0: Success + * * -#BPMP_ENODEV: Pwr limit mrq is not supported by BPMP-FW + * * -#BPMP_ENAVAIL: Invalid request parameters + */ + CMD_PWR_LIMIT_CURR_CAP = 3, +}; + +/** + * @defgroup bpmp_pwr_limit_type PWR_LIMIT TYPEs + * @{ + */ +/** @brief Limit value specifies traget cap */ +#define PWR_LIMIT_TYPE_TARGET_CAP 0U +/** @brief Limit value specifies maximum possible target cap */ +#define PWR_LIMIT_TYPE_BOUND_MAX 1U +/** @brief Limit value specifies minimum possible target cap */ +#define PWR_LIMIT_TYPE_BOUND_MIN 2U +/** @brief Number of limit types supported by mrq interface */ +#define PWR_LIMIT_TYPE_NUM 3U + +/** @} bpmp_pwr_limit_type */ + +/** + * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_QUERY_ABI + */ +struct cmd_pwr_limit_query_abi_request { + uint32_t cmd_code; /**< @ref mrq_pwr_limit_cmd */ +} BPMP_ABI_PACKED; + +/** + * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_SET + * + * Set specified limit of specified type from specified source. The success of + * the request means that specified value is accepted as input to arbitration + * with other sources settings for the same limit of the same type. Zero limit + * is ignored by the arbitration (i.e., indicates "no limit set"). + */ +struct cmd_pwr_limit_set_request { + uint32_t limit_id; /**< @ref bpmp_pwr_limit_id */ + uint32_t limit_src; /**< @ref bpmp_pwr_limit_src */ + uint32_t limit_type; /**< @ref bpmp_pwr_limit_type */ + uint32_t limit_setting; +} BPMP_ABI_PACKED; + +/** + * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_GET + * + * Get previously set from specified source specified limit value of specified + * type. + */ +struct cmd_pwr_limit_get_request { + uint32_t limit_id; /**< @ref bpmp_pwr_limit_id */ + uint32_t limit_src; /**< @ref bpmp_pwr_limit_src */ + uint32_t limit_type; /**< @ref bpmp_pwr_limit_type */ +} BPMP_ABI_PACKED; + +/** + * @brief Response data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_GET + */ +struct cmd_pwr_limit_get_response { + uint32_t limit_setting; +} BPMP_ABI_PACKED; + +/** + * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_CURR_CAP + * + * For specified limit get current power cap aggregated from all sources. + */ +struct cmd_pwr_limit_curr_cap_request { + uint32_t limit_id; /**< @ref bpmp_pwr_limit_id */ +} BPMP_ABI_PACKED; + +/** + * @brief Response data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_CURR_CAP + */ +struct cmd_pwr_limit_curr_cap_response { + uint32_t curr_cap; +} BPMP_ABI_PACKED; + +/** + * @brief Request with #MRQ_PWR_LIMIT + * + * |sub-command |payload | + * |----------------------------|---------------------------------| + * |CMD_PWR_LIMIT_QUERY_ABI | cmd_pwr_limit_query_abi_request | + * |CMD_PWR_LIMIT_SET | cmd_pwr_limit_set_request | + * |CMD_PWR_LIMIT_GET | cmd_pwr_limit_get_request | + * |CMD_PWR_LIMIT_CURR_CAP | cmd_pwr_limit_curr_cap_request | + */ +struct mrq_pwr_limit_request { + uint32_t cmd; + union { + struct cmd_pwr_limit_query_abi_request pwr_limit_query_abi_req; + struct cmd_pwr_limit_set_request pwr_limit_set_req; + struct cmd_pwr_limit_get_request pwr_limit_get_req; + struct cmd_pwr_limit_curr_cap_request pwr_limit_curr_cap_req; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** + * @brief Response to MRQ_PWR_LIMIT + * + * |sub-command |payload | + * |----------------------------|---------------------------------| + * |CMD_PWR_LIMIT_QUERY_ABI | - | + * |CMD_PWR_LIMIT_SET | - | + * |CMD_PWR_LIMIT_GET | cmd_pwr_limit_get_response | + * |CMD_PWR_LIMIT_CURR_CAP | cmd_pwr_limit_curr_cap_response | + */ +struct mrq_pwr_limit_response { + union { + struct cmd_pwr_limit_get_response pwr_limit_get_rsp; + struct cmd_pwr_limit_curr_cap_response pwr_limit_curr_cap_rsp; + } BPMP_UNION_ANON; +} BPMP_ABI_PACKED; + +/** @} PwrLimit */ +/** @endcond bpmp_th500 */ + + +/** + * @ingroup MRQ_Codes + * @def MRQ_GEARS + * @brief Get thresholds for NDIV offset switching + * + * * Platforms: TH500 onwards + * @cond bpmp_th500 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_gears_response + * @addtogroup Gears + * @{ + */ + +/** + * @brief Response to #MRQ_GEARS + * + * Used by the sender of an #MRQ_GEARS message to request thresholds + * for NDIV offset switching. + * + * The mrq_gears_response::ncpu array defines four thresholds in units + * of number of online CPUS to be used for choosing between five different + * NDIV offset settings for CCPLEX cluster NAFLLs + * + * 1. If number of online CPUs < ncpu[0] use offset0 + * 2. If number of online CPUs < ncpu[1] use offset1 + * 3. If number of online CPUs < ncpu[2] use offset2 + * 4. If number of online CPUs < ncpu[3] use offset3 + * 5. If number of online CPUs >= ncpu[3] disable offsetting + * + * For TH500 mrq_gears_response::ncpu array has four valid entries. + * + * mrq_response::err is + * * 0: gears defined and response data valid + * * -#BPMP_ENODEV: MRQ is not supported by BPMP-FW + * * -#BPMP_EACCES: Operation not permitted for the MRQ master + * * -#BPMP_ENAVAIL: NDIV offsetting is disabled + */ +struct mrq_gears_response { + /** @brief number of online CPUs for each gear */ + uint32_t ncpu[16]; +} BPMP_ABI_PACKED; + +/** @} Gears */ +/** @endcond bpmp_th500 */ /** * @addtogroup Error_Codes @@ -3047,12 +3953,18 @@ struct mrq_ec_response { #define BPMP_ENOSYS 38 /** @brief Invalid slot */ #define BPMP_EBADSLT 57 +/** @brief Invalid message */ +#define BPMP_EBADMSG 77 +/** @brief Operation not supported */ +#define BPMP_EOPNOTSUPP 95 +/** @brief Targeted resource not available */ +#define BPMP_ENAVAIL 119 /** @brief Not supported */ #define BPMP_ENOTSUP 134 /** @brief No such device or address */ #define BPMP_ENXIO 140 -/** @} */ +/** @} Error_Codes */ #if defined(BPMP_ABI_CHECKS) #include "bpmp_abi_checks.h" diff --git a/include/soc/tegra/bpmp.h b/include/soc/tegra/bpmp.h index f2604e99af09..5842e38bb288 100644 --- a/include/soc/tegra/bpmp.h +++ b/include/soc/tegra/bpmp.h @@ -6,6 +6,7 @@ #ifndef __SOC_TEGRA_BPMP_H #define __SOC_TEGRA_BPMP_H +#include <linux/iosys-map.h> #include <linux/mailbox_client.h> #include <linux/pm_domain.h> #include <linux/reset-controller.h> @@ -36,10 +37,22 @@ struct tegra_bpmp_mb_data { u8 data[MSG_DATA_MIN_SZ]; } __packed; +#define tegra_bpmp_mb_read(dst, mb, size) \ + iosys_map_memcpy_from(dst, mb, offsetof(struct tegra_bpmp_mb_data, data), size) + +#define tegra_bpmp_mb_write(mb, src, size) \ + iosys_map_memcpy_to(mb, offsetof(struct tegra_bpmp_mb_data, data), src, size) + +#define tegra_bpmp_mb_read_field(mb, field) \ + iosys_map_rd_field(mb, 0, struct tegra_bpmp_mb_data, field) + +#define tegra_bpmp_mb_write_field(mb, field, value) \ + iosys_map_wr_field(mb, 0, struct tegra_bpmp_mb_data, field, value) + struct tegra_bpmp_channel { struct tegra_bpmp *bpmp; - struct tegra_bpmp_mb_data *ib; - struct tegra_bpmp_mb_data *ob; + struct iosys_map ib; + struct iosys_map ob; struct completion completion; struct tegra_ivc *ivc; unsigned int index; diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 977c334136e9..a63de5da8124 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -34,6 +34,20 @@ enum tegra_revision { TEGRA_REVISION_MAX, }; +enum tegra_platform { + TEGRA_PLATFORM_SILICON = 0, + TEGRA_PLATFORM_QT, + TEGRA_PLATFORM_SYSTEM_FPGA, + TEGRA_PLATFORM_UNIT_FPGA, + TEGRA_PLATFORM_ASIM_QT, + TEGRA_PLATFORM_ASIM_LINSIM, + TEGRA_PLATFORM_DSIM_ASIM_LINSIM, + TEGRA_PLATFORM_VERIFICATION_SIMULATION, + TEGRA_PLATFORM_VDK, + TEGRA_PLATFORM_VSP, + TEGRA_PLATFORM_MAX, +}; + struct tegra_sku_info { int sku_id; int cpu_process_id; @@ -47,6 +61,7 @@ struct tegra_sku_info { int gpu_speedo_id; int gpu_speedo_value; enum tegra_revision revision; + enum tegra_platform platform; }; #ifdef CONFIG_ARCH_TEGRA diff --git a/include/soc/tegra/ivc.h b/include/soc/tegra/ivc.h index 4aeb77cc22c5..be45d5f5adea 100644 --- a/include/soc/tegra/ivc.h +++ b/include/soc/tegra/ivc.h @@ -4,9 +4,11 @@ */ #ifndef __TEGRA_IVC_H +#define __TEGRA_IVC_H #include <linux/device.h> #include <linux/dma-mapping.h> +#include <linux/iosys-map.h> #include <linux/types.h> struct tegra_ivc_header; @@ -15,7 +17,7 @@ struct tegra_ivc { struct device *peer; struct { - struct tegra_ivc_header *channel; + struct iosys_map map; unsigned int position; dma_addr_t phys; } rx, tx; @@ -36,7 +38,7 @@ struct tegra_ivc { * * Returns a pointer to the frame, or an error encoded pointer. */ -void *tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc); +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, struct iosys_map *map); /** * tegra_ivc_read_advance - Advance the read queue @@ -56,7 +58,7 @@ int tegra_ivc_read_advance(struct tegra_ivc *ivc); * * Returns a pointer to the frame, or an error encoded pointer. */ -void *tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc); +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, struct iosys_map *map); /** * tegra_ivc_write_advance - Advance the write queue @@ -91,8 +93,8 @@ void tegra_ivc_reset(struct tegra_ivc *ivc); size_t tegra_ivc_align(size_t size); unsigned tegra_ivc_total_queue_size(unsigned queue_size); -int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx, - dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys, +int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, const struct iosys_map *rx, + dma_addr_t rx_phys, const struct iosys_map *tx, dma_addr_t tx_phys, unsigned int num_frames, size_t frame_size, void (*notify)(struct tegra_ivc *ivc, void *data), void *data); diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index d186bccd125d..aadb845d281d 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -118,9 +118,9 @@ enum tegra_io_pad { TEGRA_IO_PAD_PEX_CLK_2, TEGRA_IO_PAD_PEX_CNTRL, TEGRA_IO_PAD_PEX_CTL2, - TEGRA_IO_PAD_PEX_L0_RST_N, - TEGRA_IO_PAD_PEX_L1_RST_N, - TEGRA_IO_PAD_PEX_L5_RST_N, + TEGRA_IO_PAD_PEX_L0_RST, + TEGRA_IO_PAD_PEX_L1_RST, + TEGRA_IO_PAD_PEX_L5_RST, TEGRA_IO_PAD_PWR_CTL, TEGRA_IO_PAD_SDMMC1, TEGRA_IO_PAD_SDMMC1_HV, |