summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJiansong Chen <Jiansong.Chen@amd.com>2020-07-14 12:34:45 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-07-15 12:46:41 -0400
commit82121d154ae19ffcf8ec482b6aaf83fdf5700ae4 (patch)
tree108e0526f5f9de044b9e15398ecb26ae6a502aea
parent922783755b52097e671b3d0bae3363223aa5ae28 (diff)
downloadlinux-82121d154ae19ffcf8ec482b6aaf83fdf5700ae4.tar.bz2
drm/amdgpu/powerplay: add smu support for navy_flounder
Now navy_flounder will reuse the smu11 driver_if header and ppt functions for sienna_cichlid. Later navy_flounder can maintain its own version if the compatibility is broken. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/amdgpu_smu.c1
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/smu_v11_0.c15
3 files changed, 16 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 4df960f0baaf..03125c8a2145 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -602,6 +602,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
smu->od_enabled =false;
break;
case CHIP_SIENNA_CICHLID:
+ case CHIP_NAVY_FLOUNDER:
sienna_cichlid_set_ppt_funcs(smu);
break;
case CHIP_RENOIR:
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 21e2cc3a526c..f06158511f93 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -31,6 +31,7 @@
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2B
/* MP Apertures */
#define MP0_Public 0x03800000
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index b939aa86accf..a7336556dc36 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -59,6 +59,7 @@ MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
+MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
#define SMU11_VOLTAGE_SCALE 4
@@ -173,6 +174,9 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
case CHIP_SIENNA_CICHLID:
chip_name = "sienna_cichlid";
break;
+ case CHIP_NAVY_FLOUNDER:
+ chip_name = "navy_flounder";
+ break;
default:
dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
return -EINVAL;
@@ -305,6 +309,9 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
case CHIP_SIENNA_CICHLID:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
break;
+ case CHIP_NAVY_FLOUNDER:
+ smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
+ break;
default:
dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
@@ -386,7 +393,8 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
- if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
+ if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
+ adev->asic_type == CHIP_NAVY_FLOUNDER) {
dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
switch (version_minor) {
case 0:
@@ -818,6 +826,11 @@ int smu_v11_0_set_tool_table_location(struct smu_context *smu)
int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
{
int ret = 0;
+ struct amdgpu_device *adev = smu->adev;
+
+ /* Navy_Flounder do not support to change display num currently */
+ if (adev->asic_type == CHIP_NAVY_FLOUNDER)
+ return 0;
if (!smu->pm_enabled)
return ret;