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| author | Chen-Yu Tsai <wens@csie.org> | 2016-09-15 23:14:01 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-09-18 21:13:35 +0200 |
| commit | 7e81bda23ac3c79b6cf747c195810900b45a77fc (patch) | |
| tree | 0de412eee606239efcb7bc4cf87087316a518851 | |
| parent | e996e2089f25b84149ae82b5ddf37a263a7fcc71 (diff) | |
| download | linux-7e81bda23ac3c79b6cf747c195810900b45a77fc.tar.bz2 | |
drm/sun4i: dotclock: Allow divider = 127
The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127,
or 6 ~ 127 if phase offsets are used. The 0 register value also
represents a divider of 1 or bypass.
Make the end condition of the for loop inclusive of 127 in the
round_rate callback.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_dotclock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c index 1b6c2253192e..3eb99784f371 100644 --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c @@ -77,7 +77,7 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate, u8 best_div = 1; int i; - for (i = 6; i < 127; i++) { + for (i = 6; i <= 127; i++) { unsigned long ideal = rate * i; unsigned long rounded; |