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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2020-04-08 18:41:55 +0300
committerAndy Shevchenko <andriy.shevchenko@linux.intel.com>2020-04-16 20:41:06 +0300
commit7e73aa90a38c8815acea7af71e285658bf5ab879 (patch)
treee77ff772f3bd99a15ccf68b3329fcd7bdc0e7a06
parent6b1c7837af0e29ad630f0ae18634f6c58a3381ee (diff)
downloadlinux-7e73aa90a38c8815acea7af71e285658bf5ab879.tar.bz2
gpio: merrifield: Better show how GPIO and IRQ bases are derived from hardware
It's a bit hard to realize what the BAR1 is for and what is the layout of the data in it. Be slightly more verbose to better show how GPIO and IRQ bases are derived from the hardware. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
-rw-r--r--drivers/gpio/gpio-merrifield.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c
index 11e6ea70568a..706687fab634 100644
--- a/drivers/gpio/gpio-merrifield.c
+++ b/drivers/gpio/gpio-merrifield.c
@@ -443,8 +443,8 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
base = pcim_iomap_table(pdev)[1];
- irq_base = readl(base);
- gpio_base = readl(sizeof(u32) + base);
+ irq_base = readl(base + 0 * sizeof(u32));
+ gpio_base = readl(base + 1 * sizeof(u32));
/* Release the IO mapping, since we already get the info from BAR1 */
pcim_iounmap_regions(pdev, BIT(1));