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authorChen-Yu Tsai <wens@csie.org>2018-11-30 13:33:28 +0800
committerChen-Yu Tsai <wens@csie.org>2018-12-03 23:54:07 +0800
commit7bb7d29cffdd24bf419516d14b6768591e74069e (patch)
tree4f377354f7056a04702531de93ab7276e154f7fe
parent01a7ea763fc46fd21692dfc070009d2c1cbc1b07 (diff)
downloadlinux-7bb7d29cffdd24bf419516d14b6768591e74069e.tar.bz2
clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
The third parent of CSI_MCLK is PLL_PERIPH1, not PLL_PERIPH0. Fix it. Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index eb5c608428fa..9341ca77c6cd 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -476,7 +476,7 @@ static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
0x134, 16, 4, 24, 3, BIT(31), 0);
-static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph0" };
+static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
0x134, 0, 5, 8, 3, BIT(15), 0);