diff options
| author | Marc Zyngier <maz@kernel.org> | 2021-11-01 19:58:42 +0000 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-02-07 16:00:41 +0000 |
| commit | 74703b13f9d2ef286ef588f29295a2fd30b5f295 (patch) | |
| tree | bb3dab71aa19a47dc704a2723fcb4348a735f56a | |
| parent | 5a6bbd1d18cabf5a680e726f0ef8f6dda0105fe8 (diff) | |
| download | linux-74703b13f9d2ef286ef588f29295a2fd30b5f295.tar.bz2 | |
dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts
Advertise the two pseudo-interrupts that tied to the two PMU
flavours present in the Apple M1 SoC.
We choose the expose two different pseudo-interrupts to the OS
as the e-core PMU is obviously different from the p-core one,
effectively presenting two different devices.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Marc Zyngier <maz@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml | 2 | ||||
| -rw-r--r-- | include/dt-bindings/interrupt-controller/apple-aic.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index 97359024709a..c7577d401786 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -56,6 +56,8 @@ properties: - 1: virtual HV timer - 2: physical guest timer - 3: virtual guest timer + - 4: 'efficient' CPU PMU + - 5: 'performance' CPU PMU The 3rd cell contains the interrupt flags. This is normally IRQ_TYPE_LEVEL_HIGH (4). diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include/dt-bindings/interrupt-controller/apple-aic.h index 604f2bb30ac0..bf3aac0e5491 100644 --- a/include/dt-bindings/interrupt-controller/apple-aic.h +++ b/include/dt-bindings/interrupt-controller/apple-aic.h @@ -11,5 +11,7 @@ #define AIC_TMR_HV_VIRT 1 #define AIC_TMR_GUEST_PHYS 2 #define AIC_TMR_GUEST_VIRT 3 +#define AIC_CPU_PMU_E 4 +#define AIC_CPU_PMU_P 5 #endif |