diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2022-02-18 00:40:21 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2022-02-21 12:06:08 +0200 |
| commit | 72935696f516e3d587838a9f0e1f82d251925840 (patch) | |
| tree | c4f0742b91c62ce9e05e35aaef5547c69f404c92 | |
| parent | 8f0991cccec93665dd6ecd88dbefd7db2b28c85e (diff) | |
| download | linux-72935696f516e3d587838a9f0e1f82d251925840.tar.bz2 | |
drm/i915/dsi: add separate init timer mask definition for ICL DSI
Having a separate definition will be useful for splitting VLV and ICL
register files.
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220217224023.3994777-2-jani.nikula@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/icl_dsi.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 479d5e1165d9..3c01565e62b2 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -570,7 +570,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, /* Program T-INIT master registers */ for_each_dsi_port(port, intel_dsi->ports) { tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); - tmp &= ~MASTER_INIT_TIMER_MASK; + tmp &= ~DSI_T_INIT_MASTER_MASK; tmp |= intel_dsi->init_count; intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 580763515b16..6f359229ecdb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9008,6 +9008,7 @@ enum skl_power_gate { #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \ _ICL_DSI_T_INIT_MASTER_0,\ _ICL_DSI_T_INIT_MASTER_1) +#define DSI_T_INIT_MASTER_MASK REG_GENMASK(15, 0) #define _DPHY_CLK_TIMING_PARAM_0 0x162180 #define _DPHY_CLK_TIMING_PARAM_1 0x6c180 |